Title:
HARDWARE-ASSISTED DESIGN VERIFICATION SYSTEM USING A PACKET-BASED PROTOCOL LOGIC SYNTHESIZED FOR EFFICIENT DATA LOADING AND UNLOADING
Document Type and Number:
WIPO Patent Application WO2002063507
Kind Code:
A3
Abstract:
A system is prvided to increase the accessibility of registers and memories in a user's design undergoing functional verificationin a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host workstation and ahardware accelerator for loading data to and unloading data from the registers and memories in a target design under verification (DUV) during logic simulation. The method and apparatus synthesizes interface logic into the DUV to provide for greater access to the registers and memories in the target DUV which is simulated with the assistance of the hardware accelerator.
Inventors:
OHKAMI TAKAHIDE
Application Number:
PCT/US2001/050388
Publication Date:
January 08, 2004
Filing Date:
October 19, 2001
Export Citation:
Assignee:
QUICKTURN DESIGN SYSTEMS INC (US)
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Foreign References:
| US5546562A | 1996-08-13 | |||
| EP0838772A2 | 1998-04-29 |
Other References:
KOCH G H ET AL: "Breakpoints and breakpoint detection in source-level emulation", ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, APRIL 1998, ACM, USA, vol. 3, no. 2, pages 209 - 230, XP002229421, ISSN: 1084-4309
KOCH G ET AL: "Debugging of behavioral VHDL specifications by source level emulation", PROCEEDINGS EURO-DAC '95. EUROPEAN DESIGN AUTOMATION CONFERENCE WITH EURO-VHDL (CAT. NO.95CB35850), PROCEEDINGS OF EURO-DAC. EUROPEAN DESIGN AUTOMATION CONFERENCE, BRIGHTON, UK, 18-22 SEPT. 1995, 1995, Los Alamitos, CA, USA, IEEE Comput. Soc. Press, USA, pages 256 - 261, XP002229422, ISBN: 0-8186-7156-4
POTKONJAK M ET AL: "Design-for-Debugging of application specific designs", 1995 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD). SAN JOSE, NOV. 5 - 9, 1995, IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, LOS ALAMITOS, IEEE COMP. SOC. PRESS, US, 5 November 1995 (1995-11-05), pages 295 - 301, XP010153072, ISBN: 0-8186-7213-7
KOCH G ET AL: "Debugging of behavioral VHDL specifications by source level emulation", PROCEEDINGS EURO-DAC '95. EUROPEAN DESIGN AUTOMATION CONFERENCE WITH EURO-VHDL (CAT. NO.95CB35850), PROCEEDINGS OF EURO-DAC. EUROPEAN DESIGN AUTOMATION CONFERENCE, BRIGHTON, UK, 18-22 SEPT. 1995, 1995, Los Alamitos, CA, USA, IEEE Comput. Soc. Press, USA, pages 256 - 261, XP002229422, ISBN: 0-8186-7156-4
POTKONJAK M ET AL: "Design-for-Debugging of application specific designs", 1995 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD). SAN JOSE, NOV. 5 - 9, 1995, IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, LOS ALAMITOS, IEEE COMP. SOC. PRESS, US, 5 November 1995 (1995-11-05), pages 295 - 301, XP010153072, ISBN: 0-8186-7213-7
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