CROSS-REFERENCE TO RELATED APPLICATION

[0001] The present application claims priority to U. S. Patent Application No. 17/941,121, filed on September 9, 2022, and titled “HARD WARE- AW ARE FEDERATED LEARNING,” the disclosure of which is expressly incorporated by reference in its entirety.

FIELD OF THE DISCLOSURE

[0002] Aspects of the present disclosure generally relate to neural networks and more particularly to techniques and apparatuses for hardware-aware federated learning.

BACKGROUND

[0003] Federated learning is an approach for collaborative training of neural networks across multiple users without gathering data at a central location. Because of the decentralized training, wherein raw data is not shared by the edge devices, federated learning is beneficial for applications in which privacy is a significant factor. Federated learning (FL) aims to address the differential privacy, continual learning, and personalization by having the edge (or end) devices perform the training locally using the data collected and transmit only the weight updates rather than the raw data.

[0004] Although FL frameworks may address these fundamental issues, performing training on the device is challenging and may be taxing in terms of memory and compute resources. As a result, some resource restricted devices may be hindered from participating in the FL. Such limitation on participation may result in model bias and decreased model performance.

SUMMARY

[0005] The present disclosure is set forth in the independent claims, respectively. Some aspects of the disclosure are described in the dependent claims.

[0006] In aspects of the present disclosure, a method for processor-implemented includes receiving, from a server, information corresponding to a first j ointly-trained artificial neural network (ANN). The method also includes determining a current hardware capability of a device for on-device training of the first j ointly-trained ANN. The method further includes transmitting, to the server, an indication of the current hardware capability. The method also includes receiving, from the server, responsive to the transmitted indication, information corresponding to a second j ointly-trained ANN), the second jointly-trained ANN being an adapted version of the first jointly-trained ANN generated based on the indication of the current hardware capability.

[0007] In other aspects of the present disclosure, a processor-implemented method includes transmitting, to one or more devices, information corresponding to a first j ointly-trained artificial neural network (ANN). The method also includes receiving, from the one or more devices, a first indication of current hardware capabilities for on- device training of the first jointly-trained ANN. The method further includes selecting a second jointly-trained ANN based on the first indication of the current hardware capabilities. The second jointly-trained ANN comprises one or more classes of the first j ointly-trained ANN, each of the one or more classes having a different computational complexity. The method also includes transmitting to the one or more devices, information corresponding to the second j ointly-trained ANN).

[0008] Other aspect of the present disclosure are directed to an apparatus. The apparatus has a memory and one or more processors coupled to the memory. The processor(s) is configured to receive, from a server, information corresponding to a first j ointly-trained artificial neural network (ANN). The processor(s) is also configured to determine a current hardware capability of a device for on-device training of the first j ointly-trained ANN. The processor(s) is further configured to transmit, to the server, an indication of the current hardware capability. The processor(s) is also configured to receive, from the server, responsive to the transmitted indication, information corresponding to a second jointly-trained ANN), the second j ointly-trained ANN being an adapted version of the first jointly-trained ANN generated based on the indication of the current hardware capability.

[0009] Other aspects of the present disclosure are directed to an apparatus. The apparatus has a memory and one or more processors coupled to the memory. The processor(s) is configured to transmit, to one or more devices, information corresponding to a first j ointly-trained artificial neural network (ANN). The processor(s) is further configured to receive, from the one or more devices, a first indication of current hardware capabilities for on-device training of the first j ointly- trained ANN. The processor(s) is still further configured to select a second jointly- trained ANN based on the first indication of the current hardware capabilities. The second jointly-trained ANN comprises one or more classes of the first jointly-trained ANN, each of the one or more classes having a different computational complexity. The processor(s) is also configured to transmit to the one or more devices, information corresponding to the second jointly-trained ANN)

[0010] Aspects generally include a method, apparatus, system, computer program product, non-transitory computer-readable medium, user equipment, base station, wireless communication device, and processing system as substantially described with reference to and as illustrated by the accompanying drawings and specification.

[0011] The foregoing has outlined rather broadly the features and technical advantages of examples according to the disclosure in order that the detailed description that follows may be better understood. Additional features and advantages will be described. The conception and specific examples disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. Such equivalent constructions do not depart from the scope of the appended claims. Characteristics of the concepts disclosed, both their organization and method of operation, together with associated advantages will be better understood from the following description when considered in connection with the accompanying figures. Each of the figures is provided for the purposes of illustration and description, and not as a definition of the limits of the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The features, nature, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout

[0013] FIGURE 1 illustrates an example implementation of designing a neural network using a system-on-a-chip (SOC), including a general-purpose processor, in accordance with certain aspects of the present disclosure. [0014] FIGURES 2A, 2B, and 2C are diagrams illustrating a neural network, in accordance with aspects of the present disclosure.

[0015] FIGURE 2D is a diagram illustrating an exemplary deep convolutional network (DCN), in accordance with aspects of the present disclosure.

[0016] FIGURE 3 is a block diagram illustrating an exemplary deep convolutional network (DCN), in accordance with aspects of the present disclosure.

[0017] FIGURE 4 is a block diagram illustrating an exemplary software architecture that may modularize artificial intelligence (Al) functions, in accordance with aspects of the present disclosure.

[0018] FIGURE 5 is a high-level block diagram illustrating an example system for hardware-aware federated learning, in accordance with aspects of the present disclosure.

[0019] FIGURES 6A and 6B are flow diagrams illustrating example processes for hardware-aware federated learning, in accordance with aspects of the present disclosure.

[0020] FIGURES 7 and 8 are flow diagrams illustrating processor-implemented methods for hardware-aware federated learning, according to aspects of the present disclosure.

DETAILED DESCRIPTION

[0021] The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0022] Based on the teachings, one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the disclosure, whether implemented independently of or combined with any other aspect of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth. In addition, the scope of the disclosure is intended to cover such an apparatus or method practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth. It should be understood that any aspect of the disclosure disclosed may be embodied by one or more elements of a claim.

[0023] The word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0024] Although particular aspects are described, many variations and permutations of these aspects fall within the scope of the disclosure. Although some benefits and advantages of the preferred aspects are mentioned, the scope of the disclosure is not intended to be limited to particular benefits, uses or objectives. Rather, aspects of the disclosure are intended to be broadly applicable to different technologies, system configurations, networks and protocols, some of which are illustrated by way of example in the figures and in the following description of the preferred aspects. The detailed description and drawings are merely illustrative of the disclosure rather than limiting, the scope of the disclosure being defined by the appended claims and equivalents thereof.

[0025] Federated learning is a decentralized form of machine learning, in which one or more local clients (e.g., end devices) collaboratively train a statistical model under the orchestration of a central device (e.g., server, serving cell, parameter server, etc.) while keeping the training data localized and maintaining privacy of the local client data. That is, machine learning algorithms, such as deep neural networks, are trained on raw data collected from multiple local datasets contained in the end devices without receiving or accessing the raw data.

[0026] Stated another way, federated learning enables users (or end devices) to train a machine learning model in a distributed fashion. Each end device may use their local dataset to train a local model and then send model updates to a central server. For example, at each round of a federated learning process, a parameter server may select a number of users and sends a copy of a global machine learning model to the selected users. Each local training iteration of the federated learning process may be referred to as an epoch and each communication round with the server may be referred to as a communication round. Each end device computes parameters of the model with its own dataset and feeds back a corresponding update (e g., weight updates) to the parameter server. The parameter server aggregates all the end device updates and determines an update for the global model by, for example, averaging the aggregated end device updates or other techniques. The parameter server broadcasts the new parameters of the global model to the selected users at the next round of the federated learning process. Because of the non-transmission of localized data, federated learning is beneficial for applications in which privacy is a significant factor.

[0027] As described, federated learning involves learning a server model, such as a neural network, with matrix tensor parameters w with a data set of N data points T> = { x ₁ ,y ₁ ), ( _N , y _w )} that is distributed across end devices S, where, for instance, T> = T) ₁ U ... U D _s without accessing the device-specific data sets directly. By defining a loss function T _s (Ds; w) per end-device, the total security risk may be written as:

[0028] This objective corresponds to empirical risk minimization over the joint data set T) with a loss £(■) for each data point. In federated learning, it is beneficial to reduce the communication costs. As such, multiple gradient updates for weights parameters w in the inner optimization of objective may be performed for each devices S, thus obtaining local models with weight parameters w _s . The multiple gradient updates may be referred to as local epochs such as an amount of data passes through the entire local data set, with an abbreviation of E. Each end device may then communicate an update corresponding to the local weight to the server. In turn, the server updates the global model at round t, for example, by averaging the parameters of the local model w ^t = [0029] Although FL frameworks may address these fundamental issues, performing training on the device is challenging and may be taxing in terms of memory and compute resources.

[0030] Because of the demand on the memory and processing capabilities, many devices may not be able to participate in FL training due to their hardware capabilities. The edge devices in FL are typically mobile devices (“UEs”) that may have inherent differences in capabilities (or characteristics). For example, hardware capabilities for different UEs may include a number and type of processors, and an amount and type (e.g., speed) of memory. Dynamic hardware capabilities may include available or projected power (e.g., battery), available or projected compute resources (e.g., based on concurrently running applications), and available or projected communication bandwidth. Thus, hardware capabilities may be dynamic. Moreover, the same UE may be capable of training different (types of) models at different times. The hardware limitation may hinder devices with lower capabilities to reap the benefits of FL. In addition, the hardware limitations may result in bias in the model because some users may be unable to utilize FL due to the limited hardware capable devices. Such limitations may result in poor model performance (e.g., incorrect classification).

[0031] To address these and other challenges, aspects of the present disclosure are directed to hardware-aware federated learning. In accordance with aspects of the present disclosure, hardware capabilities of a device participating in a federated learning model may be determined and an artificial neural network (ANN) model may be adapted based on the hardware capabilities.

[0032] FIGURE 1 illustrates an example implementation of a system-on-a-chip (SOC) 100, which may include a central processing unit (CPU) 102 or a multi-core CPU configured for hardware-aware federated learning in accordance with certain aspects of the present disclosure. Variables (e.g., neural signals and synaptic weights), system parameters associated with a computational device (e.g., neural network with weights), delays, frequency bin information, and task information may be stored in a memory block associated with a neural processing unit (NPU) 108, in a memory block associated with a CPU 102, in a memory block associated with a graphics processing unit (GPU) 104, in a memory block associated with a digital signal processor (DSP) 106, in a memory block 118, or may be distributed across multiple blocks. Instructions executed at the CPU 102 may be loaded from a program memory associated with the CPU 102 or may be loaded from a memory block 118.

[0033] The SOC 100 may also include additional processing blocks tailored to specific functions, such as a GPU 104, a DSP 106, a connectivity block 110, which may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, and the like, and a multimedia processor 112 that may, for example, detect and recognize gestures. In one implementation, the NPU is implemented in the CPU, DSP, and/or GPU. The SOC 100 may also include a sensor processor 114, image signal processors (ISPs) 116, and/or navigation module 120, which may include a global positioning system.

[0034] The SOC 100 may be based on an ARM instruction set. In an aspect of the present disclosure, the instructions loaded into the CPU 102 may comprise code to receive, from a server, information corresponding to a first j ointly-trained artificial neural network (ANN). The instructions loaded into the CPU 102 may also comprise code to determine a current hardware capability of a device for on-device training of the first jointly-trained ANN. The instructions loaded into the CPU 102 may additionally comprise code to transmit, to the server, an indication of the current hardware capability. The instmctions loaded into the CPU 102 may also comprise code to receive, from the server, responsive to the transmitted indication, information corresponding to a second jointly-trained ANN). The second j ointly-trained ANN is an adapted version of the first jointly-trained ANN generated based on the indication of the current hardware capability.

[0035] In some aspects, the instructions loaded into the CPU 102 may comprise code to transmit, to one or more devices, information corresponding to a first jointly- trained artificial neural network (ANN). The instructions loaded into the CPU 102 may also comprise code to receive, from the one or more devices, an indication of a current hardware capability for on-device training of the first jointly-trained ANN. The instructions loaded into the CPU 102 may additionally comprise code to select a second j ointly-trained ANN based on the indication of the current hardware capability. The second jointly-trained ANN includes one or more classes of the first jointly-trained ANN. Each of the one or more classes has a different computational complexity. The instructions loaded into the CPU 102 may also comprise code to transmit to the one or more devices, information corresponding to the second jointly-trained ANN) to the device.

[0036] Deep learning architectures may perform an object recognition task by learning to represent inputs at successively higher levels of abstraction in each layer, thereby building up a useful feature representation of the input data. In this way, deep learning addresses a major bottleneck of traditional machine learning. Prior to the advent of deep learning, a machine learning approach to an object recognition problem may have relied heavily on human engineered features, perhaps in combination with a shallow classifier. A shallow classifier may be a two-class linear classifier, for example, in which a weighted sum of the feature vector components may be compared with a threshold to predict to which class the input belongs. Human engineered features may be templates or kernels tailored to a specific problem domain by engineers with domain expertise. Deep learning architectures, in contrast, may learn to represent features that are similar to what a human engineer might design, but through training. Furthermore, a deep network may learn to represent and recognize new types of features that a human might not have considered.

[0037] A deep learning architecture may learn a hierarchy of features. If presented with visual data, for example, the first layer may learn to recognize relatively simple features, such as edges, in the input stream. In another example, if presented with auditory data, the first layer may learn to recognize spectral power in specific frequencies. The second layer, taking the output of the first layer as input, may learn to recognize combinations of features, such as simple shapes for visual data or combinations of sounds for auditory data. For instance, higher layers may learn to represent complex shapes in visual data or words in auditory data. Still higher layers may learn to recognize common visual objects or spoken phrases.

[0038] Deep learning architectures may perform especially well when applied to problems that have a natural hierarchical structure. For example, the classification of motorized vehicles may benefit from first learning to recognize wheels, windshields, and other features. These features may be combined at higher layers in different ways to recognize cars, trucks, and airplanes. [0039] Neural networks may be designed with a variety of connectivity patterns. In feed-forward networks, information is passed from lower to higher layers, with each neuron in a given layer communicating to neurons in higher layers. A hierarchical representation may be built up in successive layers of a feed-forward network, as described above. Neural networks may also have recurrent or feedback (also called top- down) connections. In a recurrent connection, the output from a neuron in a given layer may be communicated to another neuron in the same layer. A recurrent architecture may be helpful in recognizing patterns that span more than one of the input data chunks that are delivered to the neural network in a sequence. A connection from a neuron in a given layer to a neuron in a lower layer is called a feedback (or top-down) connection. A network with many feedback connections may be helpful when the recognition of a high-level concept may aid in discriminating the particular low-level features of an input.

[0040] The connections between layers of a neural network may be fully connected or locally connected. FIGURE 2A illustrates an example of a fully connected neural network 202. In a fully connected neural network 202, a neuron in a first layer may communicate its output to every neuron in a second layer, so that each neuron in the second layer will receive input from every neuron in the first layer. FIGURE 2B illustrates an example of a locally connected neural network 204. In a locally connected neural network 204, a neuron in a first layer may be connected to a limited number of neurons in the second layer. More generally, a locally connected layer of the locally connected neural network 204 may be configured so that each neuron in a layer will have the same or a similar connectivity pattern, but with connections strengths that may have different values (e.g., 210, 212, 214, and 216). The locally connected connectivity pattern may give rise to spatially distinct receptive fields in a higher layer, because the higher layer neurons in a given region may receive inputs that are tuned through training to the properties of a restricted portion of the total input to the network.

[0041] One example of a locally connected neural network is a convolutional neural network. FIGURE 2C illustrates an example of a convolutional neural network 206. The convolutional neural network 206 may be configured such that the connection strengths associated with the inputs for each neuron in the second layer are shared (e.g., 208). Convolutional neural networks may be well suited to problems in which the spatial location of inputs is meaningful.

[0042] One type of convolutional neural network is a deep convolutional network (DCN). FIGURE 2D illustrates a detailed example of a DCN 200 designed to recognize visual features from an image 226 input from an image capturing device 230, such as a car-mounted camera. The DCN 200 of the current example may be trained to identify traffic signs and a number provided on the traffic sign. Of course, the DCN 200 may be trained for other tasks, such as identifying lane markings or identifying traffic lights.

[0043] The DCN 200 may be trained with supervised learning. During training, the DCN 200 may be presented with an image, such as the image 226 of a speed limit sign, and a forward pass may then be computed to produce an output 222. The DCN 200 may include a feature extraction section and a classification section. Upon receiving the image 226, a convolutional layer 232 may apply convolutional kernels (not shown) to the image 226 to generate a first set of feature maps 218. As an example, the convolutional kernel for the convolutional layer 232 may be a 5x5 kernel that generates 28x28 feature maps. In the present example, because four different feature maps are generated in the first set of feature maps 218, four different convolutional kernels were applied to the image 226 at the convolutional layer 232. The convolutional kernels may also be referred to as filters or convolutional filters.

[0044] The first set of feature maps 218 may be subsampled by a max pooling layer (not shown) to generate a second set of feature maps 220. The max pooling layer reduces the size of the first set of feature maps 218. That is, a size of the second set of feature maps 220, such as 14x14, is less than the size of the first set of feature maps 218, such as 28x28. The reduced size provides similar information to a subsequent layer while reducing memory consumption. The second set of feature maps 220 may be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more subsequent sets of feature maps (not shown).

[0045] In the example of FIGURE 2D, the second set of feature maps 220 is convolved to generate a first feature vector 224. Furthermore, the first feature vector 224 is further convolved to generate a second feature vector 228. Each feature of the second feature vector 228 may include a number that corresponds to a possible feature of the image 226, such as “sign,” “60,” and “100.” A softmax function (not shown) may convert the numbers in the second feature vector 228 to a probability. As such, an output 222 of the DCN 200 is a probability of the image 226 including one or more features.

[0046] In the present example, the probabilities in the output 222 for “sign” and “60” are higher than the probabilities of the others of the output 222, such as “30,” “40,” “50,” “70,” “80,” “90,” and “100”. Before training, the output 222 produced by the DCN 200 is likely to be incorrect. Thus, an error may be calculated between the output 222 and a target output. The target output is the ground truth of the image 226 (e.g., “sign” and “60”). The weights of the DCN 200 may then be adjusted so the output 222 of the DCN 200 is more closely aligned with the target output.

[0047] To adjust the weights, a learning algorithm may compute a gradient vector for the weights. The gradient may indicate an amount that an error would increase or decrease if the weight were adjusted. At the top layer, the gradient may correspond directly to the value of a weight connecting an activated neuron in the penultimate layer and a neuron in the output layer. In lower layers, the gradient may depend on the value of the weights and on the computed error gradients of the higher layers. The weights may then be adjusted to reduce the error. This manner of adjusting the weights may be referred to as “back propagation” as it involves a “backward pass” through the neural network.

[0048] In practice, the error gradient of weights may be calculated over a small number of examples, so that the calculated gradient approximates the true error gradient. This approximation method may be referred to as stochastic gradient descent. Stochastic gradient descent may be repeated until the achievable error rate of the entire system has stopped decreasing or until the error rate has reached a target level. After learning, the DCN may be presented with new images (e.g., the speed limit sign of the image 226) and a forward pass through the network may yield an output 222 that may be considered an inference or a prediction of the DCN.

[0049] Deep belief networks (DBNs) are probabilistic models comprising multiple layers of hidden nodes. DBNs may be used to extract a hierarchical representation of training data sets. A DBN may be obtained by stacking up layers of Restricted Boltzmann Machines (RBMs). An RBM is a type of artificial neural network that can learn a probability distribution over a set of inputs. Because RBMs can learn a probability distribution in the absence of information about the class to which each input should be categorized, RBMs are often used in unsupervised learning. Using a hybrid unsupervised and supervised paradigm, the bottom RBMs of a DBN may be trained in an unsupervised manner and may serve as feature extractors, and the top RBM may be trained in a supervised manner (on a joint distribution of inputs from the previous layer and target classes) and may serve as a classifier.

[0050] Deep convolutional networks (DCNs) are networks of convolutional networks, configured with additional pooling and normalization layers. DCNs have achieved state-of-the-art performance on many tasks. DCNs can be trained using supervised learning in which both the input and output targets are known for many exemplars and are used to modify the weights of the network by use of gradient descent methods.

[0051] DCNs may be feed-forward networks. In addition, as described above, the connections from a neuron in a first layer of a DCN to a group of neurons in the next higher layer are shared across the neurons in the first layer. The feed-forward and shared connections of DCNs may be exploited for fast processing. The computational burden of a DCN may be much less, for example, than that of a similarly sized neural network that comprises recurrent or feedback connections.

[0052] The processing of each layer of a convolutional network may be considered a spatially invariant template or basis projection. If the input is first decomposed into multiple channels, such as the red, green, and blue channels of a color image, then the convolutional network trained on that input may be considered three-dimensional, with two spatial dimensions along the axes of the image and a third dimension capturing color information. The outputs of the convolutional connections may be considered to form a feature map in the subsequent layer, with each element of the feature map (e.g., 220) receiving input from a range of neurons in the previous layer (e.g., feature maps 218) and from each of the multiple channels. The values in the feature map may be further processed with a non-linearity, such as a rectification, max(0,x) Values from adjacent neurons may be further pooled, which corresponds to down sampling, and may provide additional local invariance and dimensionality reduction. Normalization, which corresponds to whitening, may also be applied through lateral inhibition between neurons in the feature map.

[0053] The performance of deep learning architectures may increase as more labeled data points become available or as computational power increases. Modem deep neural networks are routinely trained with computing resources that are thousands of times greater than what was available to a typical researcher just fifteen years ago. New architectures and training paradigms may further boost the performance of deep learning. Rectified linear units may reduce a training issue known as vanishing gradients. New training techniques may reduce over-fitting and thus enable larger models to achieve better generalization. Encapsulation techniques may abstract data in a given receptive field and further boost overall performance.

[0054] FIGURE 3 is a block diagram illustrating a deep convolutional network 350. The deep convolutional network 350 may include multiple different types of layers based on connectivity and weight sharing. As shown in FIGURE 3, the deep convolutional network 350 includes the convolution blocks 354A, 354B. Each of the convolution blocks 354A, 354B may be configured with a convolution layer (CONV) 356, a normalization layer (LNorm) 358, and a max pooling layer (MAX POOL) 360.

[0055] The convolution layers 356 may include one or more convolutional filters, which may be applied to the input data to generate a feature map. Although only two of the convolution blocks 354A, 354B are shown, the present disclosure is not so limiting, and instead, any number of the convolution blocks 354A, 354B may be included in the deep convolutional network 350 according to design preference. The normalization layer 358 may normalize the output of the convolution filters. For example, the normalization layer 358 may provide whitening or lateral inhibition. The max pooling layer 360 may provide down sampling aggregation over space for local invariance and dimensionality reduction.

[0056] The parallel filter banks, for example, of a deep convolutional network may be loaded on a CPU 102 or GPU 104 of an SOC 100 to achieve high performance and low power consumption. In alternative embodiments, the parallel filter banks may be loaded on the DSP 106 or an ISP 116 of an SOC 100. In addition, the deep convolutional network 350 may access other processing blocks that may be present on the SOC 100, such as sensor processor 114 and navigation module 120, dedicated, respectively, to sensors and navigation.

[0057] The deep convolutional network 350 may also include one or more fully connected layers 362 (FC 1 and FC2). The deep convolutional network 350 may further include a logistic regression (LR) layer 364. Between each layer 356, 358, 360, 362, 364 of the deep convolutional network 350 are weights (not shown) that are to be updated. The output of each of the layers (e.g., 356, 358, 360, 362, 364) may serve as an input of a succeeding one of the layers (e.g., 356, 358, 360, 362, 364) in the deep convolutional network 350 to learn hierarchical feature representations from input data 352 (e.g., images, audio, video, sensor data and/or other input data) supplied at the first of the convolution blocks 354A. The output of the deep convolutional network 350 is a classification score 366 for the input data 352. The classification score 366 may be a set of probabilities, where each probability is the probability of the input data including a feature from a set of features.

[0058] FIGURE 4 is a block diagram illustrating an exemplary software architecture 400 that may modularize artificial intelligence (Al) functions. Using the architecture, applications may be designed that may cause various processing blocks of an SOC 420 (for example a CPU 422, a DSP 424, a GPU 426 and/or an NPU 428) to support adaptive rounding as disclosed for post-training quantization for an Al application 402, according to aspects of the present disclosure.

[0059] The Al application 402 may be configured to call functions defined in a user space 404 that may, for example, provide for the detection and recognition of a scene indicative of the location in which the device currently operates. The Al application 402 may, for example, configure a microphone and a camera differently depending on whether the recognized scene is an office, a lecture hall, a restaurant, or an outdoor setting such as a lake. The Al application 402 may make a request to compiled program code associated with a library defined in an Al function application programming interface (API) 406. This request may ultimately rely on the output of a deep neural network configured to provide an inference response based on video and positioning data, for example. [0060] A run-time engine 408, which may be compiled code of a runtime framework, may be further accessible to the Al application 402. The Al application 402 may cause the run-time engine, for example, to request an inference at a particular time interval or triggered by an event detected by the user interface of the application. When caused to provide an inference response, the run-time engine may in turn send a signal to an operating system in an operating system (OS) space 410, such as a Linux Kernel 412, running on the SOC 420. The operating system, in turn, may cause a continuous relaxation of quantization to be performed on the CPU 422, the DSP 424, the GPU 426, the NPU 428, or some combination thereof. The CPU 422 may be accessed directly by the operating system, and other processing blocks may be accessed through a driver, such as a driver 414, 416, or 418 for, respectively, the DSP 424, the GPU 426, or the NPU 428. In the exemplary example, the deep neural network may be configured to run on a combination of processing blocks, such as the CPU 422, the DSP 424, and the GPU 426, or may be run on the NPU 428.

[0061] The application 402 (e.g., an Al application) may be configured to call functions defined in a user space 404 that may, for example, provide for the detection and recognition of a scene indicative of the location in which the device currently operates. The application 402 may, for example, configure a microphone and a camera differently depending on whether the recognized scene is an office, a lecture hall, a restaurant, or an outdoor setting such as a lake. The application 402 may make a request to compiled program code associated with a library defined in a SceneDetect application programming interface (API) 406 to provide an estimate of the current scene. This request may ultimately rely on the output of a differential neural network configured to provide scene estimates based on video and positioning data, for example.

[0062] A run-time engine 408, which may be compiled code of a Runtime Framework, may be further accessible to the application 402. The application 402 may cause the run-time engine, for example, to request a scene estimate at a particular time interval or triggered by an event detected by the user interface of the application. When caused to estimate the scene, the run-time engine may in turn send a signal to an operating system 410, such as a Linux Kernel 412, running on the SOC 420. The operating system 410, in turn, may cause a computation to be performed on the CPU 422, the DSP 424, the GPU 426, the NPU 428, or some combination thereof. The CPU 422 may be accessed directly by the operating system, and other processing blocks may be accessed through a driver, such as a driver 414-418 for a DSP 424, for a GPU 426, or for an NPU 428. In the exemplary example, the differential neural network may be configured to run on a combination of processing blocks, such as a CPU 422 and a GPU 426, or may be run on an NPU 428, if present.

[0063] According to certain aspects of the present disclosure, each of the fully connected layers 362 may be configured to determine parameters of the model based upon desired one or more functional features of the model, and develop the one or more functional features towards the desired functional features as the determined parameters are further adapted, tuned and updated.

[0064] As indicated above, FIGURES 1-4 are provided as examples. Other examples may differ from what is described with respect to FIGURES 1-4.

[0065] Aspects of the present disclosure are directed to hardware-aware federated learning. In accordance with aspects of the present disclosure, hardware capabilities of a device participating in a federated learning model may be determined and ANN models may be adapted based on the hardware capabilities.

[0066] FIGURE 5 is a high-level block diagram illustrating an example system 500 for hardware-aware federated learning, in accordance with aspects of the present disclosure. Referring to FIGURE 5, the system 500 includes a server 502 for managing a federated learning model. The system 500 also includes multiple end devices 504a-z. The end devices 504a-z may each comprise a mobile communication device such as a smartphone, a tablet, an electric vehicle, or an Internet of Things (loT) device, for example. Each of the end devices (e.g., 504a-z) may have a different hardware configuration, which may include dynamic hardware capabilities. For instance, some end devices (e.g., 504a) may be configured with graphics processing units (GPUs), neural processing units (NPUs), digital signal processors (DSPs) or may have different memory configurations. Accordingly, each of the end devices (e.g., 504a-z) may have different capabilities for operating a federated learning model or performing on-device training of the federated learning model. In accordance with aspects of the present disclosure, each of the end devices (e.g., 504a-z) may be configured to evaluate the device’s current hardware capabilities. The evaluation of current hardware capabilities, for example, may be based on physical hardware configuration (e.g., GPU, NPU, etc.) and processing capabilities. In some aspects, the current hardware capabilities may be evaluated or determined based on the current workload of the end device (e.g., 504a-z) or other performance metrics. The end devices 504a-z may send an indication of their current hardware capabilities. In turn, the server 502 may adapt an initial or full featured federated learning model for each end device (e.g., 504a-z), according to the current hardware capabilities For instance, the server 502 may compress a full featured federated learning model (e.g., via one or more of pruning, quantization, or other model compression techniques). The compressed model may be sent to the particular end device (e.g., 504a-z).

[0067] The end device (e.g., 504a-z) may continue to monitor the current hardware capabilities and may update the server 502 so that the server 502 may continue to provide a model commensurate with the current hardware capabilities. In doing so, the server 502 may provide the best level of the federated learning model that the end device (e.g., 504a-z) may accommodate. That is, server 502 may configure a federated learning model that may run on the end device with reduced or in some aspect no degradation in model performance. As such, model latency and power consumption may beneficially be reduced. Thus, user experience and enjoyment while executing the model in the background may also be improved.

[0068] Additionally, the federated learning model may be improved because more end devices may be able to participate in the federated learning process. Each of the end devices (e.g., 504a-z) may individually re-train the model on-device based on locally collected data. Each end device (e.g., 504a-z) determines model updates (e.g., weight updates) and sends such updates to the server 502. In some aspects, an end device may select a frequency at which the model updates (e.g., weight updates) are provided to the server. The frequency may be based on the current hardware capabilities. In one example, a powerful smartphone may provide weight update when it is being charged or does not have a heavy workload. In another example, an end device with less hardware capabilities such as an loT device or other battery-powered device for which battery resource is more of a concern, the frequency of updates may be adapted to keep the device running longer. The server 502, in turn, jointly-trains the federated learning model based on the updates received from the end devices (e.g., 504a-z).

[0069] FIGURES 6A and 6B are flow diagrams illustrating example processes 600 and 650 for hardware-aware federated learning, in accordance with aspects of the present disclosure. Referring to FIGURE 6A, at block 602, a server (e.g., 502 shown in FIGURE 5) may send a federated learning model to a set of participating end devices (e.g., 504a-z shown in FIGURE 5). The federated learning model may, for example, be an artificial neural network (e.g., 350 shown in FIGURE 3). The federated learning model may be a top tier model (e.g., full featured model). In some aspects, the federated learning model may be generated based on a top-level of hardware capabilities of the participating end devices. For example, the server may survey the participating end devices and may determine the top-level hardware capabilities. The server may then generate the top tier model based on the top-level hardware capabilities.

[0070] Each of the participating end devices may evaluate its current hardware capabilities. At block 604, the participating end devices may determine whether the current hardware capabilities may accommodate on-device training. In some aspects, the accommodation of on-device training may be evaluated based on certain key performance indicators (KPIs). KPIs may for instance, include inferences per second (IPS), double data rate read/write bandwidth, power consumption, memory footprint or other performance indicators. In a first example, a threshold may be applied to determine whether current hardware capabilities may accommodate on-device training (e g., > 50,000 IPS). In a second example, the server may advertise a set of models and a set of hardware specifications to run each model. As such, an end device if its current hardware capabilities comply with or meet the specifications for the advertised models and in some aspects, may determine a model best suited for its current hardware capabilities.

[0071] The end devices may determine the current hardware capabilities based on a physical hardware configuration. Additionally, in some aspects, the current hardware capabilities may be determined based on the current workload, an estimated time to completion, or other performance metrics. If the current hardware capabilities accommodate on-device training, at block 606, the device retains the model (e.g., top tier model). The device may operate the model on locally-collected data. Additionally, the device may conduct on-device training based on the locally-collected data. In turn, the device may send weight updates calculated during the on-device training to the server (not shown).

[0072] If the device (e.g., 504b) determines that the current hardware capabilities may not accommodate on-device training, then at block 608, the device may send a notification to the server. The notification may include an indication of the current hardware capabilities of the device. Alternatively, in some aspects, the end device may also indicate that its current hardware capabilities may accommodate a more complex model than the models advertised.

[0073] In response to the notification, at block 610, the server may adapt the model to adjust the model complexity. For example, in some aspects, the server may compress the top tier model. The server may compress the top tier model using one or more of pruning, quantization or other compression or model personalization techniques. The server may send the adapted model to the end device.

[0074] Thereafter, the process 600 may return to block 604 to evaluate whether the current hardware capabilities may accommodate on-device training based on the adapted model.

[0075] In this way, the process 600 may be iteratively applied until each device can successfully train the federated learning model on-device.

[0076] However, as the current hardware capabilities may vary, for example, based on hardware configuration changes or workload changes, in some aspects, the process may continually or periodically be repeated. In this way, the model complexity may be updated, and in some aspects, optimized based on the current hardware capabilities of each device.

[0077] In other aspects (not shown), the server sends a characterization of the model to a set of participating end devices, instead of the whole model. In these aspects, the end devices can determine, based on the characterization, if the end devices are capable of participating in the training rounds for the model. If so, the end devices message the server accordingly, which then sends the initial model to the capable end devices. [0078] Referring to FIGURE 6B, at block 652, the process 650 provides that a server may generate multiple classes or tiers of a federated learning model. The multiple classes or tiers of the federated learning model may have a different level of model complexity. The multiple classes or tiers of the federated learning model may be based on different hardware capabilities of the participating end devices. For example, the multiple classes of the federated learning model may be based on different dimensions such as hardware processors (e g., GPU, NPU, DSP, etc .), floating-point weights, fixed point weight quantization, edge pruning implemented, or the like.

[0079] At block 654, the end devices may determine current hardware capabilities. For instance, an end device may determine whether the current hardware capabilities may accommodate on-device training. In some aspects, the current hardware capabilities may be determined based on the physical hardware configuration.

Additionally, in some aspects, the current hardware capabilities may also be determined based on workload (e.g., applications being executed), estimated workload completion, or other performance metrics, for example. In still other aspects, the server may send the participating devices (e g., end devices 504z) an evaluation function to discover their hardware capabilities. The evaluation function may be a program executed on the end devices. The output of the program captures the hardware capabilities of the end devices at a given time, or over a duration of time. The end devices report the hardware capabilities back to the server. The end devices may use the evaluation function from time to time (periodically or event-driven) and may notify the server to negotiate a new model based on the current hardware capabilities.

[0080] At block 656, the end devices (e.g., 504z) may notify the server of its current hardware capabilities. For example, the end devices may report the hardware capabilities back to the server based on output of the evaluation function. At block 658, the server may select a class or tier of the federated learning model for each end device based on the current hardware capabilities. The selected class or model may be an estimate of a model for which the end device’s current hardware capabilities may accommodate on-device training. At block 660, the server may transmit the selected class of the model to the end devices.

[0081] Each end device may then conduct on-device training based on the received model. Accordingly, an end device may collect data and operate the local model, each of the participating devices may be re-trained (e g., according to a loss function) on- device, producing a local model update (e.g., weight updates). In turn, the device may send weight updates determined during the on-device training to the server.

Furthermore, the server may update each of the classes or tiers of the federated learning model based on the weight updates for the end devices (e.g., 504a-z). For instance, the server may update the weights for each class of the federated learning models, using a weight update methodology (e g., weight averaging). The server may also send the updated models classes to the respective devices.

[0082] The process may return to block 654 to repeat the evaluation of the current hardware capabilities. Accordingly, the server may provide a class of the model to the end devices responsive to any changes in the current hardware capabilities. In some aspects, an end device may initiate a model query to the server. For instance, where there is a change in its current hardware capabilities (e.g., change of the physical hardware configuration or a change in workload), the end device may request that the server select a new model based on the current hardware capabilities in view of the change. In one example, an end device may be able to handle a more complex model because the outstanding processes running on it previously have completed. On the other hand, the device may have new processes that are competing for hardware resources and thus may be able to accommodate a less complex model.

[0083] In some aspects, an end device may also train multiple classes or tiers of the jointly -trained ANN. For instance, where the end device has substantial processing capabilities (e g., hardware configuration with numerous processing resources) and the current workload is below a threshold value (e.g., less than ten percent of processing capacity), the end device, similar to the server, may train multiple classes or tiers of the jointly -trained ANN. Additionally, the end device may also provide such classes or tiers of the j ointly-trained ANN to the server or other end devices, for example. For instance, when the device is charging overnight, with few or no other applications competing for the end device resources, the end device may conduct multiple model trainings without impacting the device performance and user experience.

[0084] As such, the dynamic approach described may enable the end devices (e g., 504a-z of FIGURE 5) to continue to participate and reap the benefits of the federated learning framework regardless of the processes competing for the hardware resources on the devices. Moreover, the federated learning training may benefit by increasing the number of devices that may contribute weight updates and thus improve the federated learning model.

[0085] FIGURE 7 is a flow diagram illustrating a processor-implemented method 700 for hardware-aware federated learning, according to aspects of the present disclosure.

[0086] At block 702, the processor-implemented method 700 receives, from a server, information corresponding to a first jointly-trained artificial neural network (ANN). As described, for example, with reference to FIGURE 6A, a server may send a federated learning model to a set of participating end devices (e g., 504a-z shown in FIGURE 5). The federated learning model may, for example, be an artificial neural network (e.g., 350 shown in FIGURE 3). The federated learning model may be a top tier model (e.g., full featured model). In some aspects, the federated learning model may be generated based on a top-level of hardware capabilities of the participating end devices. For example, the server may survey the participating end devices and may determine the top-level hardware capabilities. The server may then generate the top tier model based on the top-level hardware capabilities. In other aspects, the information may be a characterization of the model.

[0087] At block 704, the processor-implemented method 700 determines a current hardware capability of a device for on-device training of the first jointly-trained ANN. For example, as described with reference to FIGURE 6A, the participating end devices may determine whether the current hardware capabilities may accommodate on-device training. In some aspects, the accommodation of on-device training may be evaluated based on certain key performance indicators (KPIs). KPIs may for instance, include inferences per second (IPS), double data rate read/write bandwidth, power consumption, memory footprint or other performance indicators. In some aspects, the end devices may determine the current hardware capabilities based on a physical hardware configuration. Additionally, in some aspects, the current hardware capabilities may be determined based on the current workload, an estimated time to completion, or other performance metrics. [0088] At block 706, the processor-implemented method 700 transmits, to the server, an indication of the current hardware capability. For instance, if the device (e.g., 504b) determines that the current hardware capabilities may not accommodate on- device training, the end device may send a notification to the server including an indication of the current hardware capabilities. Alternatively, in some aspects, the end device may also indicate that its current hardware capabilities may accommodate a more complex model than the models advertised. In still other aspects, the end device indicates whether the end device can participate in the FL process based on the received model information.

[0089] At block 708, the processor-implemented method 700 receives, from the server, responsive to the transmitted indication, information corresponding to information corresponding to a second jointly-trained ANN), the second j ointly-trained ANN being an adapted version of the first jointly-trained ANN generated based on the indication of the current hardware capability. For example, as described, with reference to FIGURE 6A, if the device (e.g., 504b) determines that the current hardware capabilities may not accommodate on-device training, then at block 608, the device may send a notification to the server. In some aspects, the notification may include an indication of the current hardware capabilities. Alternatively, the end device may indicate that its current hardware capabilities may accommodate a more complex model than the models advertised. In alterative aspects, if the end device sends a “not capable” message (at block 608), then the server sends information corresponding to the second model that is received at block 708. The information corresponding to the second model may be reevaluated by the end device. If, on the other hand, the end device sends more detailed hardware characteristics (at block 608), then the server can send a capability-appropriate model to the end device at block 708.

[0090] FIGURE 8 is a flow diagram illustrating a processor-implemented method 800 for hardware-aware federated learning, according to aspects of the present disclosure. Referring to FIGURE 8, at block 802, the processor-implemented method 800 transmits, to one or more devices, information corresponding to a first j ointly- trained artificial neural network (ANN).

[0091] At block 804, the processor-implemented method 800 receives, from the one or more devices, an indication of a current hardware capability for on-device training of the first jointly-trained ANN. For example, as described with reference to FIGURE 6B, at block 656, the end devices (e.g., 504z) may notify the server of its current hardware capabilities. The current hardware capabilities may be based on a physical hardware configuration, for example. Additionally, in some aspects, the current hardware capabilities may be determined based on the current workload, an estimated time to completion, or other performance metrics.

[0092] At block 806, the processor-implemented method 800 selects a second jointly -trained ANN based on the indication of the current hardware capability, the second jointly-trained ANN comprising one or more classes of the first jointly-trained ANN, each of the one or more classes having a different computational complexity. For example, as described with reference to FIGURE 6B, the server may select a class or tier of the federated learning model for each end device based on the current hardware capabilities. The selected class or model may be an estimate of a model for which the end device’s current hardware capabilities may accommodate on-device training.

[0093] At block 808, the processor-implemented method 800 transmits to the one or more devices, information corresponding to the second jointly-trained ANN to the device. If the server receives a “not capable” message (at block 804), then the server sends information corresponding to the second model at block 808. If, on the other hand, the server receives more detailed hardware characteristics (at block 808), then the server can send a capability-appropriate model to the end device at block 808.

Example Aspects

[0094] Aspect 1: A processor-implemented method, comprising: receiving, from a server, information corresponding to a first jointly-trained artificial neural network (ANN); determining a current hardware capability of a device for on-device training of the first jointly-trained ANN; transmitting, to the server, an indication of the current hardware capability; and receiving, from the server, responsive to the transmitted indication, information corresponding to a second jointly-trained ANN), the second jointly -trained ANN being an adapted version of the first jointly-trained ANN generated based on the indication of the current hardware capability.

[0095] Aspect 2: The processor-implemented method of Aspect 1, further comprising: operating the second jointly-trained ANN to generate an inference with respect to locally collected data; and re-training the second jointly-trained ANN on the device.

[0096] Aspect 3: The processor-implemented method of Aspect 1 or 2, further comprising transmitting weight updates determined in the re-training to the server.

[0097] Aspect 4: The processor-implemented method of any of the preceding Aspects, in which the device trains multiple classes of the first jointly -trained ANN, the multiple classes of the first jointly-trained ANN being specified to be accommodated by different levels of the current hardware capability.

[0098] Aspect 5: The processor-implemented method of any of the preceding Aspects, further comprising determining the current hardware capability based on one or more of a hardware configuration of the device or a current processing workload on the device.

[0099] Aspect 6: The processor-implemented method of any of the preceding Aspects, in which the first jointly-trained ANN is a more computationally complex model than the second jointly -trained ANN.

[00100] Aspect 7: The processor-implemented method of any of the preceding Aspects, in which the second jointly-trained ANN is a compressed version of the first jointly -trained ANN.

[00101] Aspect 8: The processor-implemented method of any of the Aspects 1-6, in which the second j ointly-trained ANN is one of multiple classes of the first jointly- trained ANN, the second jointly-trained ANN being selected from one of the multiple classes of the first jointly-trained ANN based on the current hardware capability.

[00102] Aspect 9: A processor-implemented method, comprising: transmitting, to one or more devices, information corresponding to a first jointly-trained artificial neural network (ANN); receiving, from the one or more devices, a first indication of current hardware capabilities for on-device training of the first jointly-trained ANN; selecting a second jointly-trained ANN based on the first indication of the current hardware capabilities, the second jointly-trained ANN comprising one or more classes of the first j ointly-trained ANN, each of the one or more classes having a different computational complexity; and transmitting to the one or more devices, information corresponding to the second jointly-trained ANN).

[00103] Aspect 10: The processor-implemented method of Aspect 9, further comprising receiving weight updates determined in a re-training process from the one or more devices.

[00104] Aspect 11 : The processor-implemented method of Aspect 9 or 10, further comprising updating the one or more classes of the first j ointly-trained ANN based on the received weight updates.

[00105] Aspect 12: The processor-implemented method of any of the Aspects 9-11, in which the current hardware capabilities of the one or more devices are based on one or more of a current hardware configuration or a current processing workload.

[00106] Aspect 13: The processor-implemented method of any of the Aspects 9-12, further comprising: receiving, from the one or more devices, a second indication of current hardware capabilities for on-device training; and selecting a third jointly-trained ANN, the third jointly-trained ANN comprising one or more classes of the first jointly- trained ANN, each of the one or more classes having a different computational complexity.

[00107] Aspect 14: An apparatus comprising: a memory; and at least one processor coupled to the memory, the at least one processor configured: to receive, from a server, information corresponding to a first j ointly-trained artificial neural network (ANN); to determine a current hardware capability of a device for on-device training of the first j ointly-trained ANN; to transmit, to the server, an indication of the current hardware capability; and to receive, from the server, responsive to the transmitted indication, information corresponding to a second jointly-trained ANN), the second j ointly-trained ANN being an adapted version of the first jointly-trained ANN generated based on the indication of the current hardware capability.

[00108] Aspect 15: The apparatus of Aspect 14, in which the at least one processor is further configured: to operate the second jointly-trained ANN to generate an inference with respect to locally collected data; and to re-train the second jointly-trained ANN on the device. [00109] Aspect 16: The apparatus of Aspect 14 or 15, in which the at least one processor is further configured to transmit weight updates determined in the re-training to the server.

[00110] Aspect 17: The apparatus of any of the Aspects 14-16, in which the device trains multiple classes of the first jointly-trained ANN, the multiple classes of the first jointly -trained ANN being specified to be accommodated by different levels of the current hardware capability.

[00111] Aspect 18: The apparatus of any of the Aspects 14-17, in which the at least one processor is further configured to determine the current hardware capability based on one or more of a hardware configuration of the device or a current processing workload on the device.

[00112] Aspect 19: The apparatus of any of the Aspects 14-18, in which the first jointly -trained ANN is a more computationally complex model than the second j ointly- trained ANN.

[00113] Aspect 20: The apparatus of any of the Aspects 14-19, in which the second j ointly -trained ANN is a compressed version of the first j ointly-trained ANN.

[00114] Aspect 21 : The apparatus of any of the Aspects 14-19 in which the second j ointly-trained ANN is one of multiple classes of the first jointly-trained ANN, the second jointly-trained ANN being selected from one of the multiple classes of the first j ointly-trained ANN based on the current hardware capability.

[00115] Aspect 22: An apparatus comprising: a memory; and at least one processor coupled to the memory, the at least one processor configured: to transmit, to one or more devices, information corresponding to a first jointly-trained artificial neural network (ANN); to receive, from the one or more devices, a first indication of current hardware capabilities for on-device training of the first jointly-trained ANN; to select a second jointly-trained ANN based on the first indication of the current hardware capabilities, the second jointly-trained ANN comprising one or more classes of the first j ointly-trained ANN, each of the one or more classes having a different computational complexity; and to transmit to the one or more devices, information corresponding to the second jointly-trained ANN). [00116] Aspect 23: The apparatus of Aspect 22, in which the at least one processor is further configured to receive weight updates determined in a re-training process from the one or more devices.

[00117] Aspect 24: The apparatus of Aspect 22 or 23, in which the at least one processor is further configured to update the one or more classes of the first jointly- trained ANN based on the received weight updates.

[00118] Aspect 25: The apparatus of any of the Aspects 22-24, in which the current hardware capabilities of the one or more devices are based on one or more of a current hardware configuration or a current processing workload.

[00119] Aspect 26: The apparatus of any of the Aspects 22-25, in which the at least one processor is further configured: to receive, from the one or more devices, a second indication of current hardware capabilities for on-device training; and to select a third jointly -trained ANN, the third jointly-trained ANN comprising one or more classes of the first jointly-trained ANN, each of the one or more classes having a different computational complexity.

[00120] In one aspect, the receiving means, the determining means, transmitting means, means for receiving the second jointly-trained ANN, and/or selecting means may be the CPU 102, program memory associated with the CPU 102, the dedicated memory block 118, fully connected layers 362, and or the routing connection processing unit 216 configured to perform the functions recited. In another configuration, the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means.

[00121] The various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to, a circuit, an application specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in the figures, those operations may have corresponding counterpart means-plus-function components with similar numbering. [00122] As used, the term “determining” encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Additionally, “determining” may include receiving (e g., receiving information), accessing (e.g., accessing data in a memory) and the like. Furthermore, “determining” may include resolving, selecting, choosing, establishing, and the like.

[00123] As used, a phrase referring to “at least one of’ a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c.

[00124] The various illustrative logical blocks, modules and circuits described in connection with the present disclosure may be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components or any combination thereof designed to perform the functions described. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[00125] The steps of a method or process described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in any form of storage medium that is known in the art. Some examples of storage media that may be used include random access memory (RAM), read only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, a hard disk, a removable disk, a CD-ROM and so forth. A software module may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media. A storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.

[00126] The methods disclosed comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.

[00127] The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may comprise a processing system in a device. The processing system may be implemented with a bus architecture. The bus may include any number of interconnecting buses and bridges depending on the specific application of the processing system and the overall design constraints. The bus may link together various circuits including a processor, machine-readable media, and a bus interface. The bus interface may be used to connect a network adapter, among other things, to the processing system via the bus. The network adapter may be used to implement signal processing functions. For certain aspects, a user interface (e.g., keypad, display, mouse, joystick, etc.) may also be connected to the bus. The bus may also link various other circuits such as timing sources, peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further.

[00128] The processor may be responsible for managing the bus and general processing, including the execution of software stored on the machine-readable media. The processor may be implemented with one or more general-purpose and/or specialpurpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry that can execute software. Software shall be construed broadly to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Machine-readable media may include, by way of example, random access memory (RAM), flash memory, read only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable Read-only memory (EEPROM), registers, magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof. The machine-readable media may be embodied in a computer-program product. The computer-program product may comprise packaging materials.

[00129] In a hardware implementation, the machine-readable media may be part of the processing system separate from the processor. However, as those skilled in the art will readily appreciate, the machine-readable media, or any portion thereof, may be external to the processing system. By way of example, the machine-readable media may include a transmission line, a carrier wave modulated by data, and/or a computer product separate from the device, all which may be accessed by the processor through the bus interface. Alternatively, or in addition, the machine-readable media, or any portion thereof, may be integrated into the processor, such as the case may be with cache and/or general register files. Although the various components discussed may be described as having a specific location, such as a local component, they may also be configured in various ways, such as certain components being configured as part of a distributed computing system.

[00130] The processing system may be configured as a general-purpose processing system with one or more microprocessors providing the processor functionality and external memory providing at least a portion of the machine-readable media, all linked together with other supporting circuitry through an external bus architecture. Alternatively, the processing system may comprise one or more neuromorphic processors for implementing the neuron models and models of neural systems described. As another alternative, the processing system may be implemented with an application specific integrated circuit (ASIC) with the processor, the bus interface, the user interface, supporting circuitry, and at least a portion of the machine-readable media integrated into a single chip, or with one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits that can perform the various functionality described throughout this disclosure. Those skilled in the art will recognize how best to implement the described functionality for the processing system depending on the particular application and the overall design constraints imposed on the overall system. [00131] The machine-readable media may comprise a number of software modules. The software modules include instructions that, when executed by the processor, cause the processing system to perform various functions. The software modules may include a transmission module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, a software module may be loaded into RAM from a hard drive when a triggering event occurs During execution of the software module, the processor may load some of the instructions into cache to increase access speed. One or more cache lines may then be loaded into a general register file for execution by the processor. When referring to the functionality of a software module below, it will be understood that such functionality is implemented by the processor when executing instructions from that software module. Furthermore, it should be appreciated that aspects of the present disclosure result in improvements to the functioning of the processor, computer, machine, or other system implementing such aspects.

[00132] If implemented in software, the functions may be stored or transmitted over as one or more instructions or code on a computer-readable medium. Computer- readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Additionally, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Thus, in some aspects, computer-readable media may comprise non-transitory computer- readable media (e.g., tangible media). In addition, for other aspects computer-readable media may comprise transitory computer- readable media (e.g., a signal). Combinations of the above should also be included within the scope of computer-readable media.

[00133] Thus, certain aspects may comprise a computer program product for performing the operations presented. For example, such a computer program product may comprise a computer-readable medium having instructions stored (and/or encoded) thereon, the instructions being executable by one or more processors to perform the operations described. For certain aspects, the computer program product may include packaging material.

[00134] Further, it should be appreciated that modules and/or other appropriate means for performing the methods and techniques described can be downloaded and/or otherwise obtained by a user terminal and/or base station as applicable. For example, such a device can be coupled to a server to facilitate the transfer of means for performing the methods described. Alternatively, various methods described can be provided via storage means (e g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc.), such that a user terminal and/or base station can obtain the various methods upon coupling or providing the storage means to the device. Moreover, any other suitable technique for providing the methods and techniques described to a device can be utilized.

[00135] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes, and variations may be made in the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.