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Title:
HARDWARE CIRCUIT FOR DEEP LEARNING TASK SCHEDULING
Document Type and Number:
WIPO Patent Application WO/2022/246639
Kind Code:
A1
Abstract:
Apparatuses, systems, and techniques for scheduling deep learning tasks in hardware are described. One accelerator circuit includes multiple fixed-function circuits that each processes a different layer type of a neural network. A scheduler circuit receives state information associated with a respective layer being processed by a respective fixed-function circuit and dependency information that indicates a layer dependency condition for the respective layer. The scheduler circuit determines that the layer dependency condition is satisfied using the state information and the dependency information and enables the fixed-function circuit to process the current layer at the respective fixed-function circuit.

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Inventors:
ZHOU YAN (CN)
ZHANG YILIN (CN)
CHEN GENG (CN)
ZHOU YAN (CN)
FAN QIFEI (CN)
GAIKWAD PRASHANT (US)
Application Number:
PCT/CN2021/095739
Publication Date:
December 01, 2022
Filing Date:
May 25, 2021
Export Citation:
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Assignee:
NVIDIA CORP (US)
ZHOU YAN (CN)
International Classes:
G06F7/57
Foreign References:
CN107844833A2018-03-27
CN108256636A2018-07-06
CN109409510A2019-03-01
US20200357099A12020-11-12
Attorney, Agent or Firm:
P. C. & ASSOCIATES (CN)
Download PDF:
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