HARMONICS REJECTION TRANSCEIVER WITH DUTY RATIO CONTROL Inventors: Hong Jiang Wael Al-Qaq Mark Forrester Zhihang Zhang [0001] This application claims priority to U.S. Provisional Patent Application No. 63/032,588, entitled, “HARMONICS REJECTION TRANSCEIVER WITH DUTY RATIO CONTROL,” filed May 30, 2020 by Jiang et al., which is incorporated by reference in its entirety. FIELD [0002] This disclosure generally relates to architectures for reducing unwanted harmonic content in transceivers. BACKGROUND [0003] In a wireless terminal, such as a cellular phone, it is common to have the undesired local oscillator clock generated clock harmonics. On the transmitter side, these clock harmonics can be mixed back to near the frequency of the desired signal through non-linearity and create near channel distortion and impact other wireless terminals nearby using similar carrier frequencies. On the receiver side, a blocker signal that is near the desired signal’s clock harmonics’ frequency can, when mixed back to baseband frequency, fall on top of the desired signal frequency through the down-conversion process and degrade the signal-to-noise and distortion ratio for the received signal. It is desirable to reduce the impact of these clock harmonics as much as possible. SUMMARY [0004] According to one aspect of the present disclosure, a transmitter having an N-phase signal source, where N is an integer greater than 2, configured to provide N input signals forming an N-phase input signal and an inverse input signal for each signal of the N input signals. The transmitter also includes a frequency synthesizer configured generate N clock signals forming an N-phase clock signal and an inverse clock signal for each signal of the N clock signals, each of the N clock signals having a phase corresponding to one of the N input signals. The transmitter also includes a harmonic rejection mixer having a first set of N mixer pairs configured to receive the N-phase input signal and the inverses of the N-phase input signal, to receive the N- phase clock signal and the inverses of the N-phase clock signal, and to generate a first output signal. Each mixer pair of the first set includes: a first mixer configured to receive and mix a corresponding one of the input signals and a corresponding one of the clock signals; and a second mixer configured to receive and mix the inverse input signal of the corresponding one of the input signals and the inverse clock signal of the corresponding one of the clock signals. The harmonic rejection mixer is configured to: form N first intermediate signals by combining, for each mixer pair of the first set, an output of the first mixer and an output of the second mixer, and combine the N first intermediate signals to form the first output signal. [0005] Optionally, in the preceding aspect, the transmitter also includes N amplifiers each configured to: receive a corresponding one of the first intermediate signals; and amplify the corresponding one of the first intermediate signals prior to combining the N first intermediate signals to form the first output signal. [0006] Optionally, in any of the preceding aspects, the harmonic rejection mixer also includes a second set of N mixer pairs configured to receive the N-phase input signal and the inverses of the N-phase input signal, to receive the N-phase clock signal and the inverses of the N-phase clock signal, and to generate a second output signal. Each mixer pair of the first set includes: a first mixer configured to receive and mix a corresponding one of the input signals and the inverse of a corresponding one of the clock signals; and a second mixer configured to receive and mix the inverse input signal of the corresponding one of the input signals and the corresponding one of the clock signals. The harmonic rejection mixer is configured to: form N second intermediate signals by combining, for each mixer pair of the second set, an output of the first mixer and an output of the second mixer, and combine the N second intermediate signals to form the second output signal. [0007] Optionally, in the preceding aspect, the transmitter also includes an inductive coupler, including: a first coil configured to receive the first output signal at a first terminal and the second output signal at a second terminal; and a second coil inductively coupled to the first coil, the second coil having a first terminal configured to provide a single ended output for the transmitter and a second terminal connected to ground. [0008] Optionally, in the preceding aspect, the transmitter also includes a power amplifier configured to receive and amplify the single ended output. [0009] Optionally, in the preceding aspect, the transmitter also includes an antenna configured to receive and transmit the single ended output. [0010] Optionally, in the any of the preceding aspects, the frequency synthesizer includes: a voltage controlled oscillator configured to generate a positive oscillator signal and a negative oscillator signal; and a local oscillator clock generator configured to generate the N clock signals forming an N-phase clock signal and the inverse clock signal for each signal of the N clock signals from the positive oscillator signal and negative oscillator signal. [0011] Optionally, in the preceding aspect, the voltage controller oscillator is configured to generate the positive oscillator signal and the negative oscillator signal with a frequency of ½ N the frequency of the N-phase clock signal. [0012] Optionally, in any of the preceding aspects, the N-phase signal source is configured to receive an input signal in in-phase/quadrature format and generate therefrom the N input signals forming an N-phase input signal and the inverse input signal for each signal of the N input signals. [0013] Optionally, in any of the preceding aspects, N equals 3. [0014] Optionally, in the preceding aspect, the frequency synthesizer is configured to generate the N clock signals with a duty cycle ratio of ½ and to generate the inverse clock signals with a duty cycle ratio of ½. [0015] Optionally, in and of the preceding aspects N equals 4. [0016] Optionally, in the preceding aspect, wherein the frequency synthesizer is configured to generate the N clock signals with a duty cycle ratio of 1/3 and to generate the inverse clock signals with a duty cycle ratio of 2/3. [0017] According to another aspect of the present disclosure, there is provided a method of transmitting a signal includes receiving N input signals forming an N-phase input signal and an inverse input signal for each signal of the N input signals and receiving N clock signals forming an N-phase clock signal, each of the N clock signals having a phase corresponding to one of the N input signals and an inverse clock signal for each signal of the N clock signals. The method also includes generating a first output signal from the N-phase input signal and the inverses of the N-phase input signal and from the N-phase clock signal and the inverses of the N-phase clock signal, by, for each of the N input signals and the inverses of the N input signals: mixing the input signal and a corresponding one of the clock signals, mixing the inverse input signal of the corresponding one of the input signals and the inverse clock signal of the corresponding one of the clock signals, and combining the mixed corresponding one of the input signals and the corresponding one of the clock signals and the mixed inverse input signal of the corresponding one of the input signals and the inverse clock signal of the corresponding one of the clock signals to from a first intermediate signal; and combining the N first intermediate signals to form the first output signal. [0018] Optionally, in the preceding aspect, the method also includes amplifying the N first intermediate signals prior to combining the N first intermediate signals to form the first output signal. [0019] Optionally, in any of the two preceding aspects, the method also generating a second output signal from the N-phase input signal and the inverses of the N-phase input signal and from the N-phase clock signal and the inverses of the N-phase clock signal, by, for each of the N input signals and the inverses of the N input signals: mixing the input signal and an inverse clock signal of a corresponding one of the clock signals; mixing the inverse input signal of the corresponding one of the input signals and the corresponding one of the clock signals; and combining the mixed corresponding one of the input signals and the inverse clock signal of the corresponding one of the clock signals and the mixed inverse input signal of the corresponding one of the input signals and the corresponding one of the clock signals to from a first intermediate signal. The method also includes combining the N second intermediate signals to form the second output signal. [0020] Optionally, in the preceding aspect, the method also includes: applying the output signal and the second output signal to a first terminal and a second terminal, respectively, of a first coil of an inductive coupler; receiving and amplifying an output from a second coil of the inductive coupler that is inductively coupled to the first coil; and transmitting the amplified output. [0021] Optionally, in any of the preceding aspects of a method of transmitting a signal, the method further comprises: receiving an input signal in in-phase/quadrature format; and generating the N input signals forming an N-phase input signal and the inverse input signal for each signal of the N input signals from the input signal. [0022] Optionally, in any of the preceding aspects of a method of transmitting a signal, the method further comprises: generating a positive oscillator signal and a negative oscillator signal by a voltage controlled oscillator configured to generate a positive oscillator signal and a negative oscillator signal; and generating the N clock signals forming an N-phase clock signal and the inverse clock signal for each signal of the N clock signals from the positive and negative oscillator signals. [0023] Optionally, in the preceding aspect the voltage controller oscillator generates the positive oscillator signal and the negative oscillator signal with a frequency of ½ N the frequency of the N-phase clock signal. [0024] Optionally, in any of the preceding two aspects: N equals 3 and the method further includes generating the N clock signals with a duty cycle ratio of ½ and to generate the inverse clock signals with a duty cycle ratio of ½; or, alternately, N equals 4 and the method further includes generating the N clock signals with a duty cycle ratio of 1/3 and to generate the inverse clock signals with a duty cycle ratio of 2/3. [0025] According to an additional aspect of the present disclosure, a receiver includes: a frequency synthesizer configured generate N clock signals forming an N- phase clock signal and an inverse clock signal for each signal of the N clock signals, where N is an integer greater than 2; and a harmonic rejection mixer. The harmonic rejection mixer includes a first set of N mixer pairs configured to receive an input signal, to receive the N-phase clock signal and the inverses of the N-phase clock signal, and to generate N first output signals forming an N-phase output signal and an inverse output signal for each signal of the N first output signals, each of the N first output signals having a phase corresponding to one of the N clock signals, the first set including: a first mixer configured to receive and mix the input signal and a corresponding one of the clock signals to generate a corresponding one of the first output signals; and a second mixer configured to receive and mix the input signal and the inverse clock signal of the corresponding one of the clock signals to generate the inversion output signal of the corresponding one of the first output signals. [0026] Optionally, in the preceding aspect, the receiver also includes an N-phase to quadrature converter configured to receive and convert the N-phase output signal into in-phase/quadrature format. [0027] Optionally, in any of the preceding aspects for a receiver, the receiver also includes N amplifiers each configured to: receive and amplify the input signal; and supply the amplified input signal to a corresponding one of the mixer pairs. [0028] Optionally, in any of the preceding aspects for a receiver, the harmonic rejection mixer further includes a second set of N mixer pairs configured to receive the input signal, to receive the N-phase clock signal and the inverses of the N-phase clock signal, and to generate N second output signals forming an N-phase output signal and an inverse output signal for each signal of the N first output signals, each of the N second output signals having a phase corresponding to one of the N clock signals, the second set including: a first mixer configured to receive and mix the input signal and the inverse clock signal of a corresponding one of the clock signals to generate a corresponding one of the second output signals; and a second mixer configured to receive and mix the input signal and the corresponding one of the clock signals to generate the inverse output signal of the corresponding one of the second output signals. [0029] Optionally, in any of the preceding aspects for a receiver, the receiver also includes an antenna configured to receive input signal. [0030] Optionally, in any of the preceding aspects for a receiver, the frequency synthesizer comprises: a voltage controlled oscillator configured to generate a positive oscillator signal and a negative oscillator signal; and a local oscillator clock generator configured to generate the N clock signals forming an N-phase clock signal and the inverse clock signal for each signal of the N clock signals from the positive oscillator signal and negative oscillator signal. [0031] Optionally, in the preceding aspect, the voltage controller oscillator is configured to generate the positive oscillator signal and the negative oscillator signal with a frequency of ½ N the frequency of the N-phase clock signal. [0032] Optionally, in any of the preceding aspects for a receiver, N equals 3. [0033] Optionally, in the preceding aspect, the frequency synthesizer is configured to generate the N clock signals with a duty cycle ratio of ½ and to generate the inverse clock signals with a duty cycle ratio of ½. [0034] Optionally, in any of the preceding aspects for a receiver, N equals 4. [0035] Optionally, in the preceding aspect, the frequency synthesizer is configured to generate the N clock signals with a duty cycle ratio of 1/3 and to generate the inverse clock signals with a duty cycle ratio of 2/3. [0036] According to another aspect of the present disclosure, there is provided a method of receiving a signal that includes: receiving an input signal; receiving N clock signals forming an N-phase clock signal and an inverse clock signal for each signal of the N clock signals, where N is an integer greater than 2; and generating N first output signals forming an N-phase first output signal and an inverse output signal for each signal of the N first output signals from the input signal and from the N-phase clock signal and the inverses of the N-phase clock signal, each of the N first output signals having a phase corresponding to one of the N clock signals, by: mixing, in a first mixer of each of N first mixer pairs, the input signal and a corresponding one of the clock signals to generate a corresponding one of the first output signals, and mixing, in a second mixer of each of the N first mixer pairs, the input signal and the inverse clock signal of the corresponding one of the clock signals to generate the inverse output signal of the corresponding one of the first output signals. [0037] Optionally, in the preceding aspect of a method of receiving a signal, the method also includes converting the N-phase first output signal into in- phase/quadrature format. [0038] Optionally, in any of the preceding aspects of a method of receiving a signal, the method also includes amplifying in each of N amplifiers the input signal; and supplying the amplified input signal from each of the N amplifiers to a corresponding one of the first mixer pairs. [0039] Optionally, in any of the preceding aspects of a method of receiving a signal, the method also includes generating N second output signals forming a second N- phase output signal and an inverse output signal for each signal of the N second output signals from an input signal and from the N-phase clock signal and the inverses of the N-phase clock signal, each of the N second output signals having a phase corresponding to one of the N clock signals, by: mixing, in a first mixer of each of N second mixer pairs, the input signal and a corresponding inverse clock signal of one of the clock signals to generate a corresponding one of the second output signals, and mixing, in a second mixer of each of the N second mixer pairs, the input signal and the corresponding one of the clock signals to generate the inverse output signal of the corresponding one of the second output signals. [0040] Optionally, in any of the preceding aspects of a method of receiving a signal, the method also includes generating a positive oscillator signal and a negative oscillator signal by a voltage controlled oscillator configured to generate a positive oscillator signal and a negative oscillator signal; and generating the N clock signals forming an N-phase clock signal and the inverse clock signal for each signal of the N clock signals from the positive and negative oscillator signals. [0041] Optionally, in the preceding aspect of a method of receiving a signal, the voltage controller oscillator generates the positive oscillator signal and the negative oscillator signal with a frequency of ½ N the frequency of the N-phase clock signal. [0042] Optionally, in any of the two preceding aspect of a method of receiving a signal, N equals 3 and the method further comprises generating the N clock signals with a duty cycle ratio of ½ and to generate the inverse clock signals with a duty cycle ratio of ½; or, alternately, N equals 4 and the method further comprises generating the N clock signals with a duty cycle ratio of 1/3 and to generate the inverse clock signals with a duty cycle ratio of 2/3. [0043] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all disadvantages noted in the Background. BRIEF DESCRIPTION OF THE DRAWINGS [0044] Aspects of the present disclosure are illustrated by way of example and are not limited by the accompanying figures for which like references indicate elements. [0045] FIG.1 illustrates a wireless network for communicating data. [0046] FIG. 2 is block diagram of a wireless communication system that can be used in a network such as in FIG.1. [0047] FIG.3 is a block diagram for a first embodiment of a transmitter illustrating improved harmonic rejection with duty ratio control. [0048] FIG. 4 is a diagram showing an embodiment for the six phase of the LO clock in the embodiment of FIG.3. [0049] FIG. 5 shows the results of a simulation for the performance of the power amplifier for the embodiment of FIG.3. [0050] FIG. 6 is a flowchart illustrating a first embodiment for the operation of a transceiver as in the embodiment of FIG.3. [0051] FIG. 7 is an embodiment of a 4-Phase transmitter system using harmonic rejection with duty ratio control. [0052] FIG.8 is a plot of the spectrum of the embodiment of FIG.7 at the output of the power amplifier. [0053] FIG.9 is a block diagram of an embodiment for a 3-Phase receiver system which rejects blockers that are located at or near 2 ^nd , 3 ^rd and 4 ^th clock harmonics. [0054] FIG. 10 is a flowchart illustrating an embodiment for the operation of a receiver as in the embodiment of FIG.9. DETAILED DESCRIPTION [0055] The present disclosure will now be described with reference to the figures, which in general relate to techniques for reducing unwanted harmonic content from transmitters and receivers. Embodiments are presented for N-Phase transmitters and receivers that can generate local oscillator clock signals from a voltage controller oscillator operating at a frequency of ½N the local oscillator frequency and that are able to reduce unwanted harmonics at a level that would typically required the voltage controller oscillator to run at N times (or higher) the local oscillator frequency through use of duty ratio control for the local oscillator clock signals. In the architectures described below, an N-Phase clock signal is generated, along with the inverses of the components of the N-Phase clock signal, and these clock signals are mixed with an N-Phase input signal and the inverses of the components of the N-Phase input signal. Rather than following the usual mixer arrangement, each component of the input signal and its inverse is respectively mixed with the corresponding phase of the clock signal and its inverse in pairs, with the pairs combined and individually amplified. In the case of a 3-Phase embodiment, for example, the duty cycle of all components of the N-Phase clock signal (and their inverse components) is 50%, resulting in the suppression of unwanted 2 ^nd order harmonics that would require a 6-Phase clock signal under previous implementations. [0056] It is understood that the present embodiments of the disclosure may be implemented in many different forms and that claims scopes should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the inventive embodiment concepts to those skilled in the art. Indeed, the disclosure is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the disclosure as defined by the appended claims. Furthermore, in the following detailed description of the present embodiments of the disclosure, numerous specific details are set forth in order to provide a thorough understanding. However, it will be clear to those of ordinary skill in the art that the present embodiments of the disclosure may be practiced without such specific details. [0057] FIG. 1 illustrates a wireless network for communicating data. The communication system 10 includes, for example, user equipment 11A-11C, radio access networks (RANs) 12A-12B, a core network 13, a public switched telephone network (PSTN) 14, the Internet 15, and other networks 16. Additional or alternative networks include private and public data-packet networks including corporate intranets. While certain numbers of these components or elements are shown in the figure, any number of these components or elements may be included in the system 10. [0058] In one embodiment, the wireless network may be a fifth generation (5G) network including at least one 5G base station which employs orthogonal frequency- division multiplexing (OFDM) and/or non-OFDM and a transmission time interval (TTI) shorter than 1 millisecond (ms) (e.g., 100 or 200 microseconds), to communicate with the communication devices. In general, a reference to base station may refer any of the eNB and the 5G base stations (gNB). In addition, the network may further include a network server for processing information received from the communication devices via the at least one eNB or gNB base station. [0059] System 10 enables multiple wireless users to transmit and receive data and other content. The system 10 may implement one or more channel access methods, such as but not limited to code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), or single-carrier FDMA (SC-FDMA). [0060] The user equipment (UE) 11A-11C are configured to operate and/or communicate in the system 10. For example, the user equipment 11A-11C are configured to transmit and/or receive wireless signals or wired signals. Each user equipment 11A-11C represents any suitable end user device and may include such devices (or may be referred to) as a user equipment/device, wireless transmit/receive unit (UE), mobile station, fixed or mobile subscriber unit, pager, cellular telephone, personal digital assistant (PDA), smartphone, laptop, computer, touchpad, wireless sensor, wearable devices or consumer electronics device. [0061] In the depicted embodiment, the RANs 12A-12B include one or more base stations 17A, 17B (collectively, base stations 17), respectively. Each of the base stations 17 is configured to wirelessly interface with one or more of the UEs 11A, 11B, 11C to enable access to the core network 13, the PSTN 14, the Internet 15, and/or the other networks 16. For example, the base stations (BSs) 17 may include one or more of several well-known devices, such as a base transceiver station (BTS), a Node-B (NodeB), an evolved NodeB (eNB), a next (fifth) generation (5G) NodeB (gNB), a Home NodeB, a Home eNodeB, a site controller, an access point (AP), or a wireless router, or a server, router, switch, or other processing entity with a wired or wireless network. [0062] In one embodiment, the base station 17A forms part of the RAN 12A, which may include other base stations, elements, and/or devices. Similarly, the base station 17B forms part of the RAN 12B, which may include other base stations, elements, and/or devices. Each of the base stations 17 operates to transmit and/or receive wireless signals within a particular geographic region or area, sometimes referred to as a “cell.” In some embodiments, multiple-input multiple-output (MIMO) technology may be employed having multiple transceivers for each cell. [0063] The base stations 17 communicate with one or more of the user equipment 11A-11C over one or more air interfaces (not shown) using wireless communication links. The air interfaces may utilize any suitable radio access technology. [0064] It is contemplated that the system 10 may use multiple channel access functionality, including for example schemes in which the base stations 17 and user equipment 11A-11C are configured to implement the Long Term Evolution wireless communication standard (LTE), LTE Advanced (LTE-A), and/or LTE Multimedia Broadcast Multicast Service (MBMS). In other embodiments, the base stations 17 and user equipment 11A-11C are configured to implement UMTS, HSPA, or HSPA+ standards and protocols. Of course, other multiple access schemes and wireless protocols may be utilized. [0065] The RANs 12A-12B are in communication with the core network 13 to provide the user equipment 11A-11C with voice, data, application, Voice over Internet Protocol (VoIP), or other services. As appreciated, the RANs 12A-12B and/or the core network 13 may be in direct or indirect communication with one or more other RANs (not shown). The core network 13 may also serve as a gateway access for other networks (such as PSTN 14, Internet 15, and other networks 16). In addition, some or all of the user equipment 11A-11C may include functionality for communicating with different wireless networks over different wireless links using different wireless technologies and/or protocols. [0066] The RANs 12A-12B may also include millimeter and/or microwave access points (APs). The APs may be part of the base stations 17 or may be located remote from the base stations 17. The APs may include, but are not limited to, a connection point (an mmW CP) or a base station 17 capable of mmW communication (e.g., a mmW base station). The mmW APs may transmit and receive signals in a frequency range, for example, from 24 GHz to 100 GHz, but are not required to operate throughout this range. As used herein, the term base station is used to refer to a base station and/or a wireless access point. [0067] Although FIG.1 illustrates one example of a communication system, various changes may be made to FIG. 1. For example, the communication system 10 could include any number of user equipment, base stations, networks, or other components in any suitable configuration. It is also appreciated that the term user equipment may refer to any type of wireless device communicating with a radio network node in a cellular or mobile communication system. Non-limiting examples of user equipment are a target device, device-to-device (D2D) user equipment, machine type user equipment or user equipment capable of machine-to-machine (M2M) communication, laptops, PDA, iPad, Tablet, mobile terminals, smart phones, laptop embedded equipped (LEE), laptop mounted equipment (LME) and USB dongles. [0068] FIG.2 is block diagram of a wireless communication system 100, such as a mobile phone or user equipment 11A-11C or base station 17, showing some of the elements discussed in the following. To transmit an output signal from the circuit elements of processor 111, a transmitter (Tx) RF/analog section 101 up-converts the output signal from an intermediate frequency (IF) range to the radio frequency (RF) range, amplifies, filters and can perform other process before supplying the transmit signal to the antenna 105. The output signal is provided to the Tx RF/analog section 101 in in-phase/quadrature (I/Q) format as in-phase and quadrature signals I _Tx and Q _Tx generated by Tx digital baseband block 107. Although Tx digital baseband block 107 is shown as a separate block from Tx RF/analog section 101 in FIG.2, depending on the embodiment these elements can be variously combined as circuit elements and implemented in hardware, firmware, software, or a combination of these. [0069] Signals are received by the antenna 105 and supplied to a receiver (Rx) RF/analog section 102. Rx section 102 performs any needed or wanted signal processing, such as down-conversion from the radio frequency (RF) range to the intermediate frequency (IF) range and filtering, before passing the signal on to other elements on the device represented at processor 111. In the embodiment of FIG.2, the output of the Rx RF/analog section 102 is in I/Q format and the Rx digital baseband section 117 converts this to the receive signal supplied to the processor. Although the Rx digital baseband section 117 is shown as a separate block from Rx RF/analog section 102 in FIG.2, depending on the embodiment these elements can be variously combined as circuit elements and implemented in hardware, firmware, software, or a combination of these. Additionally, although FIG. 2 represents the Tx RF/analog section 101 and Rx section RF/analog 102 as separate elements, depending on the embodiment, the transmitter and receiver paths can share many elements or be embodied as a combined transceiver. In the following, “transceiver” may be used generally to refer a combined transmitter/receiver, separate transceiver and receiver sections, or an embodiment in which one or more components (e.g., local oscillators) are shared between the transmitter and receiver. [0070] In a transceiver, such as a mobile telephone, it is common to have undesired clock harmonics generated from the local oscillator. On the transmitter side, these clock harmonics can be mixed back to near the frequency of the desired signal through non-linearities in and creates near channel distortion (e.g., CIM2, CIM3, CIM5, where CIMx is the x ^th order counter inter-modulation) and also impact other wireless terminals nearby using near-by carrier frequencies. On the receiver side, a blocker signal can be used near the desired signal’s clock harmonics frequency, but when mixed back to the baseband frequency this can fall on top of the desired signal frequency when down-converter and degrade the received signal. [0071] Typically, some of these unwanted harmonics can be removed through multi-phase (N-Phase) mixer design, with an appropriate choice of N, where the higher the value N, the more harmonics that will be removed. So, a high value of N is preferred for harmonic suppression. However, for an N-Phase mixer design, a high value of N requires the oscillator (e.g., a voltage controller oscillator, or VCO) to run at a high frequency. (Typically, the minimum VCO frequency is fLO*N/2, where fLO is the local oscillator carrier frequency.) This results in high power consumption in the VCO and can make the VCO design challenging. [0072] The following presents embodiments for a Harmonic Rejection Mixer (HRM) mixer that can run at lower value of N, thus reducing the VCO frequency requirement, while rejecting more harmonics than a traditional N-Phase HRM. [0073] To transmit a quadrature IQ signal (a signal in in-phase/quadrature, or IQ, format), a minimum of N=3, i.e. 3-Phase system, is used. To minimize the VCO frequency as much as possible, a first set of embodiments use a 3-Phase transmitter system as an example to demonstrate aspects of the concepts presented in the following discussion. [0074] To generate the 3 phases in a standard 3-Phase system, the VCO clock needs to run at least at 1.5X the local oscillator (LO) clock rate while using both the rising and falling edges of the VCO signal. For example, if the carrier frequency is 7.15GHz, the VCO frequency needs to be at least 7.15*1.5=10.725GHz. In practice, the lower harmonics (e.g., 2 ^nd harmonics, 3 ^rd harmonics) are more critical than higher harmonics in terms of which harmonics should be rejected. Even though the 3-Phase system is efficient, a typical 3-Phase implementation does not reject even order local oscillator clock harmonics, such as the strong 2 ^nd harmonic. This even order clock harmonics will mix back to near desired transmitter signal frequency through even order post mixer non-linearities, which eventually creates CIM2 and CIM4. The following embodiments presented here adjust to duty ratio of the LO clocks so that the transceiver can reject more clock harmonics. [0075] More specifically, in a first set of embodiments the VCO is allowed to run at 1.5X for 3-Phase system example, while rejecting 2 ^nd , 3 ^rd and 4 ^th order LO clock related harmonics. This can provide clock harmonic performance that is similar to a 6-Phase system (corresponding to N=6 and requiring the VCO to run at 3X), but at half the VCO frequency. FIG.3 is a bock diagram for such an embodiment. [0076] FIG.3 is a block diagram for a first embodiment of a transmitter illustrating improved harmonic rejection with duty ratio control. Considering FIG.3 at a high level, an IQ source 107, which can be generated inside the Tx digital baseband block 107 of FIG.2, provides the signal to be transmitted. The signal from IQ source 107 is in I/Q format, and, as described below, is converted into 3-Phase signal, whose components provide the source signal in an analog 3-Phase format to harmonic rejection block HRM 200. A frequency synthesizer 230 supplies the set of clock signals to HRM 200. The output of HRM 200 is supplied to antenna 105 through a set of variable gain amplifiers VGA 221-i and VGA 223-i, inductive coupler 251, power amplifier PA 253, and filter 255. [0077] In the block of frequency synthesizer 230, VCO 231 generates, in this embodiment, a differential output of positive output p and negative output n at a frequency of 1.5X the local oscillator frequency, fVCO=1.5*fLO. A duty ratio adjustment block 233 adjusts the VCO signal’s duty ratio so that LO clock generation block 235 can be generated to have a ½ (50%) duty cycle ratio, instead of a traditional 1/3 (33) duty cycle ratio LO clocks. (It will be understood that in an actual circuit, a clock signal generated to have a 50% duty cycle, for example, will in practice differ slightly from this nominal value: for example, the waveforms illustrated below with respect to FIG. 5 illustrate an example where the actual signal is for a duty cycle of 49.7878%.) For the output of the LO clock generation block 235, the final LO signals are the 3-Phase signal of clk0, clk120 and clk240 and the complementary LO clock signals clk0b, clk120b and clk240b, which are also generated to have a 50% duty ratio. [0078] With the final LO clock duty ratio at 50%, counting all three phases, the output of the frequency synthesizer 230 is an overlapping LO clock system. With a typical passive mixer design used in cellular applications, these overlapping clock signals would create cross-talk, which is undesired. To get around the issue, the architecture of the embodiments presented here use a segmented variable gain amplifier (VGA), group mixers into a different segment for each segmented VGA, and groups these elements so that each segment does not have any LO clock overlapping. The summation of the different segments happens at the output of the VGAs. In a two sided differential embodiment, this technique can be applied to both the positive side (p side) and negative side (n side), as illustrated in FIG.3. [0079] The three p side intermediate outputs of HRM 200 each go to a corresponding one of VGA 221-1, VGA-2221-2, or VGA-3221-3. The input of each of these VGAs is the combined output from a pair of mixers receiving one of the LO clock signals and the inverse of that LO clock signal: the input of VGA 221-1 is the combined output of mixer 201 receiving clk0 and mixer 202 receiving clk0b to produce a first p side intermediate output; the input of VGA 221-2 is the combined output of mixer 203 receiving clk120 and mixer 204 receiving clk120b to produce a second p side intermediate output; and the input of VGA 221-3 is the combined output of mixer 205 receiving clk240 and mixer 206 receiving clk240b to produce a second p side intermediate output. As noted parenthetically above each of these mixers in FIG. 3, each of these LO signals has a duty cycle of 50%. Although the duty cycle ratio is 50% for each LO signal and their inverses, the mixers are paired so that the LO signals in each pair are complementary and non-overlapping. [0080] A similar arrangement is used on the n side intermediate outputs of HRM 200, each going to one of a corresponding VGA 223-1, VGA-2223-2, or VGA-3223- 3. The input of each of these VGAs is the combined output from a pair of mixers receiving one of the LO clock signals and the inverse of that LO clock signal: the input of VGA 223-1 is the combined output of mixer 211 receiving clk0 and mixer 212 receiving clk0b to produce a first n side intermediate output; the input of VGA 223-2 is the combined output of mixer 213 receiving clk120 and mixer 214 receiving clk120b to produce a second n side intermediate output; and the input of VGA 223-3 is the combined output of mixer 215 receiving clk240 and mixer 216 receiving clk240b to produce a third n side intermediate output. As again noted parenthetically above each of these mixers, each of these LO signals has a duty cycle of 50%. [0081] Each segmented path inside the HRM 200 uses complementary signals (i.e. clk0 and clk0b pair, clk120 and clk120b pair, clk240 and clk240b pair) so that the sum of the non-overlapping clocks’ duty ratio in each segment to be 100%. For example, in the first segment of mixers 201 and 202 that combine to provide the input for VGA 221-1, clk0 and clk0b are non-overlapping with 50% duty ratio for each so, the total duty cycle between them is 100%. With the total of 100% non-overlapping clocks, the mixer switching on/off can happen properly so that the baseband IQ signal are properly sampled by LO clocks. [0082] FIG. 4 is a diagram showing an embodiment for the six phase of the LO clock in the embodiment of FIG.3, i.e., clk0/clk120/clk240/clk0b/clk120b/clk240b from LO clock generation block 235. As seen, the components of the 3-Phase LO signal clk0/clk120/clk240 are overlapping. However, the clk0/clk0b pair, the clk120/clk120b pair, and the clk240/clk240b pair are non-overlapping. [0083] Returning to FIG. 3, in the signal path, the IQ data from IQ source 107 is digitally converted to 3-Phase baseband signals (0, 120, 240) in conversion block 243. Then three digital to analog converters (DACs) DAC_0245-1, DAC_120245-2, and DAC_240245-3 convert the 3-Phase digital signals to analog signals, which are then filtered through low pass filters (LPFs) LPF_0247-1, LPF_120247-2, and LPF_240 247-3 to remove unwanted distortions and noise. Typically, the DACs and LPFs are differential circuit to be relatively immune from other noise source inside the transceiver. This means in addition to 0, 120 and 240 signals, the complementary signals (180, 300, 60) are also created and provided to HRM 200. Together, the elements 107, 243, 245-1, 245-2, 245-3, 247-1, 247-2, and 247-3 form an N=3 phase signal source 241. [0084] The harmonic rejection mixer (HRM) 200 combines the LPFs’ outputs and LO clocks to generate the RF output. As illustrated in FIG.3, on the p side the 0 and 180 outputs from LPF 247-1 are respectively mixed with clk0 at mixer 201 and clk0b at mixer 202; the 120 and 300 outputs from LPF 247-2 are respectively mixed with clk120 at mixer 203 and clk120b at mixer 204; and the 240 and 60 outputs from LPF 247-3 are respectively mixed with clk240 at mixer 205 and clk240b at mixer 206. The n side is similarly arranged, but with the outputs from each of the LPFs swapped: the 180 and 0 outputs from LPF 247-1 are respectively mixed with clk0 at mixer 211 and clk0b at mixer 212; the 300 and 120 outputs from LPF 247-2 are respectively mixed with clk120 at mixer 213 and clk120b at mixer 214; and the 60 and 240 outputs from LPF 247-3 are respectively mixed with clk240 at mixer 215 and clk240b at mixer 216. [0085] The RF output from the p side mixers is amplified by the VGAs 221-1, 221- 2, and 221-3 and combined to provide a p side output signal from HRM 200, with the RF from the n side mixers similarly amplified by the VGAs 223-1, 223-2, and 223-3 and combined to provide an n side output signal from HRM 200. To convert the RF output from the VGAs to a single ended output, an inductive coupler 251 can be used, with the combined p side output and the combined n -side output connected across a first coil of inductive coupler 251 and the second coil of the inductive coupler 251 having one side set at ground and the other side providing a single-ended signal at the output. A power amplifier PA 253 amplifies the single-ended output and the PA output is filtered through a RF filter 255 to remove unwanted distortions. Finally, the filtered RF output is fed to the antenna 105. [0086] FIG.5 shows the results of a simulation for the performance at the output of the power amplifier for the embodiment of FIG.3. More specifically, the plot of FIG.5 plots the output of the 3-Phase power amplifier output in decibels (dB), normalized so that the desired transmitter (Tx) signal is at 0dB, as a function of frequency. In the plot of FIG. 5, the desired signal frequency (about 1.2288x10 ⁸ Hz) is chosen to be lower than an actual RF target frequency for fast simulation purpose. In the simulation, the duty cycle is taken as 49.7878%, rather than the exact 50%, to represent the less than ideal operation of the circuit of FIG.3 that might occur in an actual implementation. In addition to the desired Tx signal, at a somewhat lower frequency are a peak due to LO leakage, down by about -60dB, and a peak due to image distortion, down by over -80dB. [0087] With respect to the harmonics, for the second order counter inter-modulation FIG.5 shows a peak on the positive side CIM2p down by -80dB and the peak on the negative side CIM2n down by about -70dB. If the duty cycle ratio were closer to 50%, the CIM2 would be reduced further. There is no third order CIM3 peak and the only other significant spike is for CIM5, which is down about -100dB. Consequently, the simulation results of FIG. 5 illustrate that the performance at the output at output of power amplifier PA 253 of the 3-Phase HRM architecture of FIG.3 with LO clock duty ratio adjustment and the segmented VGA structure can achieve harmonic rejection that is comparable to a standard 6-Phase HRM. The spectrum of this system shows the levels of all CIM distortion are sufficiently low for cellular applications. [0088] FIG. 6 is a flowchart illustrating a first embodiment for the operation of a transceiver as in the embodiment of FIG. 3. At 601 the HRM receives the N components of the N-phase input signal and the inverse of these input signals. In the 3-Phase embodiment of FIG.3, this includes the components (0, 120, 240) of the 3- Phase input signal and the inverses (180, 300, 60) of these input signals. In the embodiment of FIG.3, these signals are generated from the I/Q signal of IQ source 107 by the 3-Phase conversion block, DACs 245-1, 245-2, 245-3 and LPFs 247-1, 247-2, 247-3. [0089] At 603 the frequency synthesizer 230 generates, and HRM 200 receives, the LO clock signals. The LO clock signals include the N components of an N-Phase clock signal and the inverse clock signals of these N components. In the 3-Phase embodiments of FIG. 3, these are the clock signals Clk0, Clk120, and Clk240 and there inverses Clk0b, Clk120b, and Clk240b, all of which have a duty ratio of ½ (50%). Although the flowchart of FIG.6 presents its elements is particular sequence, it will be understood that these can all be performed concurrently (i.e., 601, 603, and following elements are both going at the same time) to generate the output signal when the circuit of FIG.3 is transmitting. [0090] At 605, for each N-phase input signal, the input signal is mixed with the corresponding clock signal. For example, in the embodiment of FIG.3, on the n-side of HRM 200 the inputs signal components (0, 120, 240) are respectively mixed with the components of the 3-Phase (clk0, clk120, clk240) in mixers 201, 203 and 205. For the two-sided embodiment of FIG.3, the inverse inputs signal components (180, 300, 60) are respectively mixed with (clk0, clk120, clk240) in mixers 211, 213, and 215. [0091] At 607, for each N-phase input signal, the components of the inverse of the N-Phase input signal is mixed with the inverses of corresponding clock signal. For example, in the embodiment of FIG. 3, on the n-side of HRM 200 the inputs signal components (180, 300, 60) are respectively mixed with (clk0b, clk120b, clk240b) in mixers 202, 204 and 206. For the two-sided embodiment of FIG.3, the inverse of the inverse (i.e., the components themselves) inputs signal components (0, 120, 240) are respectively mixed with (clk0b, clk120b, clk240b) in mixers 212, 214, and 216. [0092] At 609,for each of the N-phase input signal components the mixed signal pairs from 605 and 607 are combined to form a set of N intermediate outputs. In the 3-Phase embodiment of FIG.3, this corresponds to combining the outputs of the mixer pairs (201, 202), (203, 204), and (205, 206) to obtain the N p side intermediate outputs. In a two sided embodiment as in FIG.3, to also generate N n side intermediate outputs, the outputs of the mixer pairs (211, 211), (213, 214), and (215, 216) are combined. [0093] At 611, the N intermediate outputs are individually amplified and then combined to provide an output signal. In the 3-Phase embodiment of FIG.3, on the p side this corresponds to amplifying outputs mixer pairs (201, 202), (203, 204), and (205, 206) in respective VGAs 221-1, 221-2, and 221-3. The outputs of these VGAs are then combined to provide the output signal for the p side of HRM 200. In the two sided embodiment of FIG. 6, on the n side the outputs mixer pairs (211, 212), (213, 214), and (215, 216) are amplified in respective VGAs 223-1, 231-2, and 231-3, with the outputs of these VGAs are then combined to provide the output signal for the n side of HRM 200. [0094] The output signals are then transmitted in 613. In a two sided embodiment like FIG.3, the p side and n side outputs are converted to a single sided output at the coils of inductive coupler 251. The single sided output is then amplified in power amplifier PA 253, filtered at filter 255, and then transmitted from antenna 105. [0095] FIG. 7 is an embodiment of a 4-Phase transmitter system using harmonic rejection with duty ratio control. In a typical 4-Phase transmitter system, the non- overlapping clock the duty ratio is 25%. This typical 4-Phase system suffers CIM3 issues because of the existence of the 3 ^rd harmonics in the 4-Phase system. If the duty ratio of the LO clocks is instead adjusted to be 1/3 (33.33%), the 3 ^rd harmonics will not be presented in the LO signal to start with, which means this modified 4-Phase system will not have appreciable 3 ^rd order harmonics and thus no major CIM3 concerns. [0096] The embodiment of FIG. 7 extends the mixer and VGA related circuit elements of FIG.3 to a 4-Phase system. The other elements of the transmitter (LPFs, DACs, LO generation) circuit can be derived from the 3-Phase example discussed earlier, where the LO clocks and associated complementary clocks are 4-Phase in this example. In frequency synthesizer 730, VCO has a frequency of N/2 times the LO frequency, where N is the number of LO clock phases, so that for the N=4 embodiment fVCO=2*fLO. FIG. 4 is again a two sided embodiment with the p and n outputs of VCO 731 going to the duty ration adjustment block, giving the p side component a duty ration of 1/3 and the n side component a complementary duty ratio of 2/3. The LO clock generation block 735 then generates the components Clk0, Clk90, Clk180, and Clk270 of the N-Phase clock signal, all with a 1/3 (33.33%) duty cycle ratio, and the inverses of these components Clk0b, Clk90b, Clk180b, and Clk270b will have a 2/3 duty cycle ration. It should be noted that in this embodiment that inverses are not redundant (that is, Clk0 is not the same as Clk180b, for example) as the inverses have a duty cycle of 66.67%. Taken together, each LO component and its inverse will have a combined duty cycle of 100%. [0097] For the 4-Phase input signal, signal from the IQ source 107 provides the I component to DAC_I 745-1, which in turn provides the two sided input I and Ib to filter LPF_I 747_1 to filter the in-phase input to HRM 700. The Q component goes to DAC_Q 745-2, which in turn provides the two sided input Q and Qb to filter LPF_I 747_2 to filter the quadrature input to HRM 700. In the 4-Phase embodiment, as I and Ib are 180 degrees out of phase, and Q and Qb are 180 degree out of phase, together the four signals (I, Q, Ib, Qb) form a 4-Phase input signal, the inverse of which is (Ib, Qb, I, Q), so that only two DACs and two LPFs are used. (That is, the inverse of the components of the 4-Phase input signal do not need to be separately generated, just re-arranged from the components of the 4-Phase input signal.) Together, the elements 107, 745-1, 745-2, 747-1, and 747-2 form an N=4 phase signal source 741. [0098] Similarly to FIG.3, on the n side of HRM 700, the 4-Phase input signals (I, Q, Ib, Qb) are respectively mixed with the corresponding components of the 4-Phase LO clock signals (Clk0, Clk90, Clk180, Clk270) in mixers 701, 703, 705, and 707. The inverses (Ib, Qb, I, Q) of the 4-Phase input signals are respectively mixed with the corresponding inverse components (Clk0b, Clk90b, Clk180b, Clk270b) of the 4-Phase LO clock signals in mixers 702, 704, 706, and 708. To generate the four intermediate p side outputs, the outputs from the mixer pairs (701, 702), (703, 704), (705, 706), and (707, 708) are mixed and amplified in corresponding VGA 721-1, 721-2, 721-3, and 721-4. The outputs of the p side VGAs are then combined to generate the p side output. [0099] On the n side of HRM 700, the inverse components (Ib, Qb, I, Q) 4-Phase input signals are respectively mixed with the corresponding components of the 4- Phase LO clock signals (Clk0, Clk90, Clk180, Clk270) in mixers 711, 713, 715, and 717. The 4-Phase input signals (I, Q, Ib, Qb) are respectively mixed with the corresponding inverse components (Clk0b, Clk90b, Clk180b, Clk270b) of the 4-Phase LO clock signals in mixers 712, 714, 716, and 718. To generate the four intermediate n side outputs, the outputs from the mixer pairs (711, 712), (713, 714), (715, 716), and (717, 718) are mixed and amplified in corresponding VGA 723-1, 723-2, 723-3, and 723-4. The outputs of the side VGAs are then combined to generate the n side output. [00100] As the embodiment of FIG. 7 is again a 2 sided embodiment, the p and n side outputs are connected across a first coil of inductive coupler 751, with the second coil providing the single sided output to power amplifier PA 753. The amplified output from PA 753 can then be filtered at 755 and transmitted from antenna 105. [00101] FIG.8 is a plot of the spectrum of the embodiment of FIG.7 at the output of the power amplifier PA 753. The plot of FIG.8 is arranged similarly to the plot of FIG. 5, with frequency in Hzx10 ⁸ versus the level in dB, normalized so that the desired output is at 0dB. There is LO leakage, down by about -80dB, and CIM distortion for the 3 ^rd harmonic on both the p and n sides and for the 5 ^th harmonic. In all cases, the peaks are reduced, by about -65dB for CIM3n, about -85dB for CIM3p, and by over - 100dB for CIM5. The CIM3n and CIM3p peaks are generated through higher order harmonics, but their levels are low enough to not create major concerns in cellular applications. [00102] With respect to the duty ratio adjustment, such as in block 235 of the embodiment of FIG.3 and the block 735 of FIG.7, to reject even harmonics (as in 3- Phase example of FIG.3 to reject the 2 ^nd harmonic), the LO clock duty ratio is set to be 50% in the duty ratio adjustment block. Depending on cases, in the original un- adjusted LO clock as used in previous approaches, the duty ratio would be 33.333% or 66.667%. To reject 3 ^rd harmonic (as in the 4-Phase example of FIG. 7), the LO clock duty ratio is set to be 33.333% or 66.667%. In the original un-adjusted LO clock as used in previous approaches, the duty ratio is typically 25%. [00103] The architecture described above in the examples above allows the duty ratio adjusted to allow an N-Phase HRM to cancel more harmonics than a standard N- Phase HRM with the same value of N. To achieve a similar performance in the reduction of clock harmonics performance, the previous implementations require that the N-Phase system to run at higher value N, which means a higher VCO frequency. For example, the embodiment of FIG.3 uses a 3-Phase system in which the VCO runs at 1.5x the local oscillator frequency, whereas to achieve similar performance the prior approach would need to operate as a 6-Phase system in which the VCO runs at 3X the local oscillator frequency. Similarly, the embodiment of FIG. 7 can operate with fVCO=2*fLO, whereas to obtain similar performance the previous approach would need an 8-Phase system with fVCO=4*fLO. [00104] The architectures described above for transmitters, such as Tx section 101 of FIG.2, and also be applied to receivers, such as RX section 102 of FIG.2. Much of the discussion above for the transmitter case follows over to the receiver case. Although discussed separately, the transceiver embodiments and receiver embodiments can share many components or be embodied in a combined transceiver. [00105] FIG.9 is a block diagram of an embodiment for a 3-Phase receiver system which rejects blockers that are located at or near 2 ^nd , 3 ^rd and 4 ^th clock harmonics. The overall structure of the receiver embodiment of FIG. 9 is similar to the transmitter embodiment of FIG.3, except, roughly speaking, with the signal paths reversed. A 4- Phase receiver system can similarly be based on the transmitter embodiment of FIG. 7. In the receiver embodiments presented here, a segmented low noise amplifier (LNA) is used to avoid overlapping cross-talk. [00106] More specifically, the frequency synthesizer 930 can be of the same or a similar structure to frequency synthesizer 230 of FIG. 3, where VCO 931, duty ratio adjustment block 933, and LO clock generation block 935 can operate as described above with respect to the corresponding elements 231, 233, and 235. [00107] Rather than receiving a 3-Phase input signal and inverse signals of its components, HRM 900 now generates a 3-phase output signal (0, 120, 240) and, as FIG. 9 is again a two sided embodiment, the inverse values (180, 300, 60) of the 3- phase output. The complimentary output signal pairs act as the differential inputs to a set of low pass filters and analog to digital converters. More specifically, the (0, 180) pair are the differential input to LPF_0947-1, whose output then goes to ADC_0945- 1 to give the (single ended) first (0 degree phase) component of the 3-phase output. Similarly, the (120, 300) pair are the differential input to LPF_120947-2, whose output then goes to ADC_120945-2 to give the (single ended) second (120 degree phase) component of the 3-phase output; and the (240, 60) pair are the differential input to LPF_240947-3, whose output then goes to ADC_240945-3 to give the (single ended) third (240 degree phase) component of the 3-phase output. [00108] The inputs to HRM 900 are from a segmented LNA of LNA 921-1, LNA-2 921-2, and LNA-3921-3, each connected to receive a signal from the antenna 105 by way of RF filter 955. The output of each of LNAs 921-1, 921-2, and 921-3 is differential, with the p side output of each going to a corresponding pair of p side mixers in HRM 900 and n side output of each going to the corresponding pair of n side mixers in HRM 900. [00109] Within HRM 900, the p side output from LNA 921-1 goes to the mixer pair 901, 902 to be respectively mixed with Clk0 and Clk0b to generate the differential output component 0, 180. The n side output from LNA 921-1 goes to the mixer pair 911, 912 to be respectively mixed with Clk0 and Clk0b to generate the reversed differential output component 180, 0. Similarly, the p side output from LNA 921-2 goes to the mixer pair 903, 904 to be respectively mixed with Clk120 and Clk120b to generate the differential output component 120, 300. The n side output from LNA 921- 1 goes to the mixer pair 913, 914 to be respectively mixed with Clk120 and Clk120b to generate the reversed differential output component 300, 120. The p side output from LNA 921-3 goes to the mixer pair 905, 906 to be respectively mixed with Clk240 and Clk240b to generate the differential output component 240, 60. The n side output from LNA 921-3 goes to the mixer pair 915, 916 to be respectively mixed with Clk240 and Clk240b to generate the reversed differential output component 60, 240. [00110] FIG. 10 is a flowchart illustrating an embodiment for the operation of a receiver as in the embodiment of FIG. 9. At 1001, an input signal is received. Referring to the embodiment of FIG.9, the input signal is received by the antenna 105 and then goes to the segmented LNA 921-1, 921-2, and 921-3, with the differential outputs supplied to the p side and n side of HRM 900. [00111] At 1003 the frequency synthesizer 930 generates, and HRM 900 receives, the LO clock signals. The LO clock signals include the N components of an N-Phase clock signal and the inverse clock signals of these N components. In the 3-Phase embodiment of FIG.9, these are the clock signals Clk0, Clk120, and Clk240 and there inverses Clk0b, Clk120b, and Clk240b, all of which have a duty cycle ratio of ½ (50%). [00112] At 1005, for each component of the N-phase clock signal, the corresponding input signal from the LNAs is mixed with the clock signal to generate to the corresponding N-Phase output signal. In the embodiment of FIG.9, on the p side the output of LNA 921-1 goes to the mixer 901, where it is mixed with Clk0 to provide the 0 phase component of the output signal. Similarly, the p side the output of LNA 921- 2 goes to the mixer 903, where it is mixed with Clk120 to provide the 120 phase component of the output signal, and the p side output of LNA 921-3 goes to the mixer 905, where it is mixed with Clk240 to provide the 240 phase component of the output signal. Together, the output of mixers 901, 903, and 905 provide the 3-Phase output signal. [00113] At 1007, for each component of the N-phase clock signal, the corresponding input signal from the LNAs is mixed with the inverse clock signal to generate to the corresponding invers N-Phase output signal. In the embodiment of FIG.9, on the p side the output of LNA 921-1 goes to the mixer 902, where it is mixed with Clk0b to provide the 180 phase component of the inverse output signal. Similarly, the p side the output of LNA 921-2 goes to the mixer 904, where it is mixed with Clk120b to provide the 300 phase component of the inverse output signal, and the p side output of LNA 921-3 goes to the mixer 906, where it is mixed with Clk240b to provide the 60 phase component of the inverse output signal. Together, the output of mixers 902, 904, and 906 provide the inverse of the components of the 3-Phase output signal. [00114] For a two sided embodiment as in FIG. 9, the n side outputs of the LNAs are also mixed with the N-Phase clock signals components and their inverses. In the embodiment of FIG.9, on the n side the output of LNA 921-1 goes to the mixer 911, where it is mixed with Clk0 to provide the 180 phase component of the output signal. Similarly, the n side the output of LNA 921-2 goes to the mixer 913, where it is mixed with Clk120 to provide the 300 phase component of the output signal, and the n side output of LNA 921-3 goes to the mixer 915, where it is mixed with Clk240 to provide the 60 phase component of the output signal. Together, the output of mixers 901, 903, and 905 provide the inverse of the 3-Phase output signal for a differential embodiment. [00115] In the embodiment of FIG. 9, on the n side the output of LNA 921-1 also goes to the mixer 912, where it is mixed with Clk0b to provide the 0 phase component of the n side inverse output signal. Similarly, the n side the output of LNA 921-2 goes to the mixer 914, where it is mixed with Clk120b to provide the 120 phase component of the n-side inverse output signal, and the n side output of LNA 921-3 goes to the mixer 916, where it is mixed with Clk240b to provide the 240 phase component of the n side inverse output signal. Together, the output of mixers 912, 914, and 916 provide the inverse of the 3-Phase output signal for the n side. [00116] As described above, for the receiver embodiments as well as the transmitter embodiments, the described architecture allows for the use of a lower VCO frequency to achieve similar harmonics performance as for traditional higher N-Phase (larger value of N) systems. Unlike traditional N-Phase systems, the LO clocks are overlapping clock, but combined in pairs in a way that allows for the use of a lower N value. [00117] The technology described herein can be implemented using hardware, firmware, software, or a combination of these. The software or firmware used can be stored on one or more processor readable storage devices to program one or more of the blocks of FIGs. 3-10 to perform the functions described herein. The processor readable storage devices can include computer readable media such as volatile and non-volatile media, removable and non-removable media. By way of example, and not limitation, computer readable media may comprise computer readable storage media and communication media. Computer readable storage media may be implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Examples of computer readable storage media include RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information, and which can be accessed by the components described above. A computer readable medium or media does (do) not include propagated, modulated or transitory signals. [00118] Communication media typically embodies computer readable instructions, data structures, program modules or other data in a propagated, modulated or transitory data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term “modulated data signal” means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as RF and other wireless media. Combinations of any of the above are also included within the scope of computer readable media. [00119] In alternative embodiments, some or all of the software or firmware can be replaced by dedicated hardware logic components. For example, and without limitation, illustrative types of hardware logic components that can be used include Field-programmable Gate Arrays (FPGAs), Application-specific Integrated Circuits (ASICs), Application-specific Standard Products (ASSPs), System-on-a-chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), special purpose computers, etc. In one embodiment, software (stored on a storage device) implementing one or more embodiments is used to program one or more processors. The one or more processors can be in communication with one or more computer readable media/ storage devices, peripherals and/or communication interfaces. [00120] It is understood that the present subject matter may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this subject matter will be thorough and complete and will fully convey the disclosure to those skilled in the art. Indeed, the subject matter is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the subject matter as defined by the appended claims. Furthermore, in the following detailed description of the present subject matter, numerous specific details are set forth in order to provide a thorough understanding of the present subject matter. However, it will be clear to those of ordinary skill in the art that the present subject matter may be practiced without such specific details. [00121] Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatuses (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable instruction execution apparatus, create a mechanism for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. [00122] The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The aspects of the disclosure herein were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure with various modifications as are suited to the particular use contemplated. [00123] For purposes of this document, each process associated with the disclosed technology may be performed continuously and by one or more computing devices. Each step in a process may be performed by the same or different computing devices as those used in other steps, and each step need not necessarily be performed by a single computing device. [00124] Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.