Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
HIERARCHICAL MEMORY ADDRESS DECODING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2020/136394
Kind Code:
A2
Inventors:
SHARMA PRATIK (IN)
Application Number:
IB2018/060572
Publication Date:
July 02, 2020
Filing Date:
December 24, 2018
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
SHARMA PRATIK (IN)
International Classes:
G06F12/00; G11C11/00
Download PDF:
Claims:
Claims

Following is the claim for this invention:-

1. In this invention we have a hierarchical memory address decoding circuit where there are dedicated memory address decoders for memories like Cache, Random Access Memory, Hard Disk memory, Solid State Disk memory, etc. Each decoder in the integrated circuit is aware of the static memory address space of the corresponding type of memory. Also all the decoders can perform multi-bit shift operations in a single bus cycle on a given memory address. Also here the Central Processing Unit(CPU) can be provided with a special instruction set to decode various types of memory addresses. The above novel technique of maintaining and using a hierarchical memory address decoding circuit for decoding various types of memory addresses is the claim for this invention.

Description:
Hierarchical Memory Address Decoding Circuit

In this invention we have a hierarchical memory address decoding circuit where there are dedicated memory address decoders for memories like Cache, Random Access Memory, Hard Disk memory, Solid State Disk memory, etc. Each decoder in the integrated circuit is aware of the static memory address space of the corresponding type of memory. Also all the decoders can perform multi-bit shift operations in a single bus cycle on a given memory address. Also here the Central Processing Unit(CPU) can be provided with a special instruction set to decode various types of memory addresses.




 
Previous Patent: HIGHLY AVAILABLE MESSAGE QUEUE

Next Patent: A LEVITATING BED