Flip con structure is a novel chip integration technique which provides about 90% increase in packaging densities in a hybrid integrated circuit.

Background Art With small satellite missions becoming a reality and preliminary studies undergoing, it was felt that new packaging technologies which could provide higher functional integration in small volumes shall be pursued. So far users are provided with single layer and multilayer hybrid circuits using conventional chip and wire technology.

Though some developmental work has been carried out in areas of multilayer structures and photo etchable high density interconnections for increasing interconnect densities, it did not provide major improvements. In a conventional hybrid integrated circuit, interconnections are carried out by wire bonding. In a flip chip assembly of hybrid integrated circuit, the chip is reversed and directly attached to a substrate in face down configuration. The interconnections between bond pads of chip and metalized conductor are provided through metallic bumps formed on the chip.

The high density hybrid integrated circuit package according to the invention provides a three dimensional packaging by mounting two chips on over the other on a substrate.

Disclosure of the invention Accordingly the present invention provides a high density hybrid integrated circuit package comprising an insulator substrate with a metalised pattern for interconnecting the integrated circuit configuration an integrated circuit flip chip consisting of plurality of semiconductor devices and provided with gol stud bumps for providing inter- 1 boy thermal compression bonding, the said stud bumps on the flip clip being bonded to the metalised portions on the ceramic substrate, an integrated circuit top chip consisting of plurality of semiconductor devices being fixed with an epoxy to the top portion of the flip chip and the electrical connections from the top chip to the metalised pattern on the substrate being taken through goldwires bonded to the top chip and the metalised pattern on the substrate.

The invention also provides a method of manufacturing a high density hybrid integrated circuit package as described hereinabove, comprising the steps of preparing an insulator substrate with a metalised pattern to form the desired integrated circuit configuration, preparing an integrated circuit flip chip and an integrated circuit top chip consisting of plurality of semiconductor devices, making gold stud bumps on the flip chip, attaching the flip chip by thermal compression bonding between the gold stud bumps on the flip chip and the corresponding connection points on the top chip to the respective connection points in the metalised pattern on the substrate, fixing the top chip on top of the flip chip by means of an epoxy adhesive, bonding gold wire to the connection points on the top chip to the respective connection points in the metalised pattern on the substrate to obtain the hybrid integrated circuit package.

Preferably the space between the flip chip and the insulator substrate is filled with an epoxy and cured for a stable attachment between the flip chip and the substrate. The insulator substrate is preferably a ceramic substrate.

Thus in the hybrid integrated circuit package according to the invention, the integrated circuit in the flip chip and the integrated circuit in the top chip are mounted back to back. The connections from the integrated circuit in the flip chip is provided by chip bonding and the connections from the integrated circuit in the top chip is provided by wire bonding.

In order to make the interconnection between the flip chip and the substrate the chip is tempererily glued to a substrate with an adhesive. Then using gold wire and thermosonic wire bonder, the gold stud bumps are formed on the chip at the point of connections. Typically, the gold wire used is of about 1.0 mil diameter, 1 to 3% elongation and tensil strength of about 12 gms. The gold stud bumps are made preferably keeping the temperature of the substrate at 125 to 150°C, bonding force between 40 to 100 gms and the bonding time between 40 to 80 millisecond. The chip is removed from the substrate after the gold stud bumps are formed on the chip. The flip chip with gold stud bumps are aligned with the metalised pattern on the substrate which is heated preferably at a temperature of 240 to 260°C and bonded to the respective connection points in the metalised pattern on the substrate by thermal compression bonding.

The bonded chip is tested for interconnection integrity.

The method of chip bonding and wire bonding are well known in the art and the optimum parameters to obtain good result are well known for person skilled in the art. Various thermal compression bonding machines and thermosonic wire bonders are used in the art.

After the flip chip is bonded to the substrate, an epoxy is dispensed from the side to fill the space between the flip chip and the substrate. It is preferable to use a two part epoxy with a viscosity typically in the range of 1800 to 2000 cps, so that, the space between the flip chip and substrate is filled by capillary action. It is then cured at a temperature preferably in the range of 80 to 150°C for a period of 30 to 120 minutes in an oven. The top chip is attached with non-conductive epoxy adhesive to the flip chip and cured preferably at a temperature in the range of 80 to 150°C for 30 to 120 minutes in an oven.

Interconnections from top chip to the metalised pattern on the substrate is done by thermosonic wire bonding using gold wire. Typically 1.0 mil diameter gold wire having an elongation of 1 to 3%, tensile strength of 12 gms is used for wire bonding. Preferably substrate temperature may be kept at 125 to 150°C, bonding force may be kept at 40 to 100 gms and bonding period may be kept between 40 to 80 milli second. The wire bonding is widely used in the art and the parameters are well known to persons skilled in the art.

In order to protect the wire bonding from mechanical stress the structure is preferably encapsulated using a known glob top encapsulant. It provides additional heat desipation to the package.

Brief Description of the Drawings The invention will now be described with reference to the accompanying drawings : Fig. 1 : shows the structure of a conventional wire bonded integrated circuit.

Fig. 2 shows the structure of a conventional chip bonded integrated circuit.

Fig. 3 shows the structure of a high density hybrid integrated circuit package according to the invention.

Fig. 4 shows the process flow chart illustrating the manufacturing steps.

Best mode for carrying out the invention The structure of integrated circuit package using wire bonding is shown in fig. 1 and that using chip bonding is shown in fig. 2. The connections from the integrated circuit chip (2) to the metalised pattern (5) on the substrate (1) is provided through gold wire (4) bonded to the chip (2) and to the connection points to the substrate (1). The chip (2) is fixed to the substrate (1) by epoxy adhesive (8). In the embodiment shown in fig. 2, the integrated circuit chip is a flip chip (7) with gold stud bumps (6) for bonding to the metalised pattern on the substrate (1). The flip chip (7) is bonded on the metalised pattern on the substrate (1). The space between the flip chip (7) and the substrate (1) is filled with epoxy (3) to provide better adherence of the flip chip (7) to the substrate (1). The integrated circuit package according to the invention is shown in fig. 3. An integrated circuit flip chip (7) is provided with gold stud bumps (6) for bonding to the metalised pattern on the substrate for providing interconnection. The space between the flip chip (6) and the substrate (1) is filled with epoxy (3) for better adherence of the flip chip (7) to the substrate. An integrated circuit top chip (9) is fixed to the integrated circuit flip chip (7) with an epoxy adhesive (8). The interconnections from the top chip (9) to the metalised pattern (5) on the substrate is done by means of gold wire (4) bonded to the connection points on the top chip (9) and the connection points in the metalised pattern (5) on the substrate (1).

The method steps for manufacturing the high density hybrid integrated circuit package is illustrated in figure 4. A high density interconnect substrate is prepared on an insulator substrate (1) preferably on a ceramic substrate, by metalising the desired pattern. The stud bumps (6) are formed on the flip chip (7) for bonding with the substrate (1) and thus providing interconnections. The flip chip (7) is bonded with the metalised pattern on the substrate (1) and tested. Then an epoxy (3) is dispensed from the side to fill the space between the flip chip (7) and substrate (1) followed by curing. The top chip (9) is attached to the flip chip by an epoxy adhesive (8). The connections from the top chip (9) to the metalised pattern (5) on the substrate is made through gold wires (4) by wire bonding.

The high density integrated circuit package is tested for interconnection integrity. In order to protect the wire bonds from mechanical stress the hybrid integrated circuit package may preferably be encapsulated using a suitable encapsulant. This will also help heat descipation characteristics of the device.

Industrial Applicability The hybrid integrated circuit package according to the invention can be used with advantage in portable electronic gadgets, personal computers, disc drives, high density memories and various other commercial applications. The invention provides hybrid integrated circuit package with higher packaging density with reduced effective weight.

The tests conducted on the hybrid integrated circuit package according to the invention provided excellent results and the structure is found rugged and reliable.