Title:
HIGH ELECTRON MOBILITY TRANSISTOR
Document Type and Number:
WIPO Patent Application WO/2024/047783
Kind Code:
A1
Abstract:
A high electron mobility transistor according to an embodiment of the present disclosure comprises a heterojunction structure that includes a GaN channel layer in which two recesses are formed with a predetermined gap therebetween. The high electron mobility transistor further comprises a regrowth layer that is formed so as to bury the recesses, source and drain electrodes that are in ohmic contact with the regrowth layer, and a gate electrode that is disposed at a location between the two recesses of the GaN channel layer with a gate insulating film interposed therebetween. The regrowth layer is configured to include a first GaN layer that is doped with Si at a relatively high concentration, and one or a plurality of second GaN layers that are doped with Si at a relatively low concentration, the second GaN layer being formed inside the first GaN layer.
Inventors:
TAKETOMO MIKIHIRO (JP)
MORI KUNIHIKO (JP)
YANAGITA MASASHI (JP)
MORI KUNIHIKO (JP)
YANAGITA MASASHI (JP)
Application Number:
PCT/JP2022/032732
Publication Date:
March 07, 2024
Filing Date:
August 31, 2022
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L29/778; H01L21/338; H01L29/812
Foreign References:
| JP2018206994A | 2018-12-27 | |||
| JP2020072218A | 2020-05-07 | |||
| CN104465746A | 2015-03-25 | |||
| JP2017059671A | 2017-03-23 |
Attorney, Agent or Firm:
TSUBASA PATENT PROFESSIONAL CORPORATION (JP)
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