Title:
HIGH-FREQUENCY DELAY-LOCKED LOOP AND CLOCK PROCESSING METHOD FOR SAME
Document Type and Number:
WIPO Patent Application WO/2016/050211
Kind Code:
A1
Abstract:
A high-frequency delay-locked loop and a clock processing method for the high-frequency delay-locked loop. The high-frequency delay-locked loop comprises a DLL circuit and a DCC circuit that are sequentially connected in series, and a pulse generating circuit. The pulse generating circuit is used for generating a clock having a fixed pulse width. The fixed pulse width is a high-level width of the clock having the fixed pulse width and is not smaller than a minimum pulse width required by the DLL circuit. Further, the fixed pulse width enables a low-level width of the clock having the fixed pulse width to be not smaller than the minimum pulse width required by the DLL circuit. The clock having the fixed pulse width is input into the DLL circuit.
Inventors:
MINZONI ALESSANDRO (CN)
Application Number:
PCT/CN2015/091198
Publication Date:
April 07, 2016
Filing Date:
September 30, 2015
Export Citation:
Assignee:
SHANDONG SINOCHIP SEMICONDUCTORS CO LTD (CN)
International Classes:
H03L7/08
Foreign References:
| CN104242921A | 2014-12-24 | |||
| CN204119209U | 2015-01-21 | |||
| CN104283550A | 2015-01-14 | |||
| CN103546151A | 2014-01-29 | |||
| CN102638246A | 2012-08-15 | |||
| CN101087132A | 2007-12-12 | |||
| CN102055436A | 2011-05-11 | |||
| US20100091591A1 | 2010-04-15 |
Attorney, Agent or Firm:
PEKSUNG INTELLECTUAL PROPERTY LTD. (CN)
北京北翔知识产权代理有限公司 (CN)
北京北翔知识产权代理有限公司 (CN)
Download PDF: