BACKGROUND ART As widely known in the relevant field, an operation amplifier, referred to as an "Op-Amp,"is applied in diverse manners as a basic component of the output unit of a driver for the liquid crystal display, analog-digital converter, digital-analog converter, switched capacitor filter, continuous time filter, and so forth. Fundamentally, the Op- Amp has the wide gain bandwidth. The Op-Amp may be distinguished as having the single output structure or the complete differential structure. The single output Op- Amps may further be classified into two types. One is the two stage structure, which has one level with a differential input amplifier and a level transition unit, and the gain level, connected parallel by the common source structure. The other one is the structure to cascode the common gate transistor.

Figure 1 illustrates the conventional structure of an Op-Amp. Such Op-Amp comprises a differential input amplifier 102, a level shift & single-ended gain circuit 104, and an output buffer 106. In Figure 1, Vi+ and Vi-illustrate differential input signals and Vout illustrates the output signal.

An Op-Amp of the folded cascode type structure, widely used as an output unit of a liquid crystal display, includes a differential input amplifier 102 composed of a couple of common source PMOS transistors for input of differential signals. The

drain outputs of the PMOSs are inputted to the source of a couple of common gate NMOS transistors and amplified and, then, transferred to an output buffer 106.

Figure 2 illustrates an output buffer shown in Figure 1. The illustrated output buffer is of the common drain (source follower) type. The Op-Amp having the output buffer of the common drain type has strengths in that it has a low output resistance and operates as Class B. However, the voltage gain is low. Moreover, in case of an Op- Amp for driving a liquid crystal display which uses the high voltage power source and the general single P-Well (or N-Well) process, the output voltage range is limited by the body effect of the NMOS (PMOS) MN3.

Figure 3 illustrates another type of an output buffer shown in Figure 1. The illustrated output buffer is of the common source output unit type. Such Op-Amp having the common source output buffer has the great voltage gain but has the high output resistance. Moreover, at the time of operation, the PMOS transistor (Mp3) and the NMOS transistor (MN3) are all turned on, causing the electric power waste.

DISCLOSURE OF THE INVENTION The object of the present invention is to provide a high-gain low-power operation amplifier for driving a flat display, which minimizes the quiescent current at the output buffer so as to minimize the static current of the operation amplifier, and increases the open circuit voltage gain.

In order to achieve the above objects, the operation amplifier for driving a flat display according to a preferred embodiment of the present invention, composed of a differential input amplification and level shift unit and an output unit, receives differential signals, amplifies them by high gain, and outputs the amplified signals.

The output unit of the operation amplifier comprises a phase splitter for receiving the

output from the differential input amplification and level shift unit and outputting the positive phase signal and the negative phase signal of the inputted signal, and an output buffer for buffering the output from the phase splitter.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates the structure of a conventional folded cascode operation amplifier.

Figure 2 is an illustration of a conventional output buffer shown in Figure 1.

Figure 3 is another illustration of a conventional output buffer shown in Figure 1.

Figure 4 is a preferred embodiment of the present invention's operation amplifier.

Figure 5 is another preferred embodiment of the present invention's operation amplifier.

Figure 6 illustrates the operation of the output unit of the operation amplifier according to preferred embodiments of the present invention. Figure 6a illustrates the operation at the time when the positive signal is inputted into the phase splitter and Figure 6b illustrates the operation at the time when the negative signal is inputted.

Figure 7 illustrates an equivalent circuit of the output unit of the operation amplifier according to preferred embodiments of the present invention.

Figure 8 is a graph illustrating the simulation result in the frequency dimension after the MOS resistance has been added according to the present invention.

Figure 9 illustrates the modeling of data lines of the driver load, the LCD panel, so as to confirm the results of the present invention.

Figure 10 is a graph illustrating the simulating result in the time dimension of the operation amplifier according to the present invention.

Figure 11 illustrates a graph of the simulation result in the time dimension at input conditions that are different from those in Figure 10.

**Description of reference numerals for important parts of the drawings** 410: Differential input amplification and level shift unit 420,520: Output unit BEST MODE FOR CARRYING OUT THE INVENTION Reference will now be made in detail to preferred embodiments of the present invention as illustrated in the accompanying drawings.

The operation amplifier ("Op-Amp") for driving a flat display according to a preferred embodiment of the present invention combines the folded cascode structure and a new output buffer structure so as to minimize the quiescent current at the output buffer unit and maximize the open circuit voltage gain. Also, the present invention includes a phase splitter in the output buffer unit and uses the common drain and the common source together by using only the PMOSs at the load driving unit for the operation as Class B. Thus, differently from the conventional Op-Amp having the output buffer of the common drain (source follower) method in which the voltage gain is 1, the present invention's Op-Amp for driving a flat display has the voltage gain.

Thus, the open circuit DC gain of the overall Op-Amp is increased.

Figure 4 is a circuit diagram of the Op-Amp for driving a flat display according to a preferred embodiment of the present invention. In Figure 4, the differential amplification and level shift unit 410 and the output unit 420 are illustrated.

Figure 5 is a modified circuit of the Op-Amp for driving a flat display of Figure 4.

The Op-Amp described in Figure 5 lowers the output resistance by using the feedback circuit at the output unit 520.

As shown in Figure 4, the differential amplification and level shift unit 410 is the PMOS transistor of the common source in which MI and M2 receive the differential signals (Vjl, Vj2) to the gate. This is the typical folded cascode structure in which the drain output of the PMOS is connected to the source of the NMOS transistors (M5, M6) of the common gate. The operation of such folded cascode structure has been widely know. Thus, the explanation of such operation is omitted here. Now, the improved operations of the output unit according to the preferred embodiment of the present invention will be explained.

The output unit 420 of the Op-Amp for driving a flat display according to a preferred embodiment of the present invention comprises the phase splitter (M I I-M 16) and the output buffer (M17, M18). The phase splitter comprises the PMOS and NMOS transistors Mll-M16. The output buffer comprises a couple of PMOS transistors or a couple of NMOS transistors (M17, M18). The conventional output buffer would comprise a pair of transistors, of which if one is PMOS, the other one is NMOS. In contrast, according to the preferred embodiment of the present invention, the two transistors must be either PMOS or NMOS for the Class B operation.

Figure 6 is a diagram to illustrate the output unit's operations of the Op-Amp for driving a flat display according to a preferred embodiment of the present invention.

Figure 6a illustrates the phase splitter's operations when the positive signal has been inputted. Figure 6b illustrates the operations when the negative signal has been inputted.

As shown in Figure 6, when the high signal is inputted in Vol, the high signal is generated at the source of the common drain amplifier Vu node. Thus, M18'sIVGSI decreases to become close to the cutoff state. At the drain of the common source amplifier VD, the low signal is generated. Thus, M17's IVGSI increases to the saturation. If the low signal is inputted in Vo], the low signal is generated at the source of the common drain amplifier Vu node. Thus, M18 becomes the saturation state. At VD, the high signal is generated. Thus, M17 is cutoff. As explained above, M18 and M17 are not simultaneously turned"ON"by the output of the phase splitter. Therefore, the Op-Amp for driving a flat display according to a preferred embodiment of the present invention operates as Class B and the output quiescent current may be minimized.

On the other hand, when the Op-Amp for driving a flat display shown in Figure 6 operates at the small signals, Mll-M18 become the multi-pole system combining the common source amplifier and the common drain amplifier. Thus, the circuit becomes unstable at the feedback operation. Accordingly, the present invention included the capacitance Cp for the frequency compensation between the output buffer and the phase splitter and the PMOS transistor M19 as a linear resistance (See Figure 4 and Figure 5) so as to operate the Op-Amp for driving a flat display with stability. The output buffer between Vol and Vo2 may be illustrated as Figure 7's equivalent circuit model.

As shown in Figure 7, if the open circuit DC gain between Vo] and Vo2 is-Ao, the Miller capacitance at the input unit of Figure 4 becomes Cp (l+ Ao). Rol, because it is also the folded cascode output resistance, becomes very large. Thus, the dominant pole arises and, therefore, the equivalent circuit may be expressed as the

following Equation 1.

<Equation 1> <BR> <BR> <BR> <BR> 1<BR> <BR> Ao) cpRol Vo2 (jW)-A# Vo1(ju) # 1 + jw(1 + A0)CpR01 As shown in the foregoing Equation 1, the output buffer system may be deemed as a system of the first degree. It operates with stability even in a feedback circuit regardless of load resistance.

Figure 8 illustrates the result of a simulation in the frequency area after the addition of the MOS resistance. Figure 8 shows the unit gain frequency of 1. lMHz and the phase margin of about 60 degrees.

Figure 9 is a schematic diagram illustrating the modeling of the data line of the driving load, LCD panel, for confirming the performance of the present invention's Op- Amp for driving a flat display. In Figure 9, resistance elements (RLSRLN) and capacitance elements (CL1#CLN) of the data line are illustrated as the distributed circuit model. So as to confirm the operation of the present invention's Op-Amp for driving a flat display in the time dimension, the load conditions of 127pF and 5ko are constituted at the output unit for the divided driving of a 30-inch LCD panel.

Figure 10 illustrates the result of the time dimension simulation after the supply of 1.2-8.8 V square pulse (for the display of black images) at the input unit.

Figure 10 shows the slew rate of 6.8V/Ilsec. It may be confirmed that 0.1% settling time is less than 3 p. sec. As shown in the transient current waveform of Figure 10, it is confirmed that the Class-B operation is conducted for display of any images.

On the other hand, in case of a large area LCD, the load conditions vary greatly in accordance with the manufacture material and process of the panel. Thus, simulations of tracking errors at the final line time of the voltage Vu, set at the output unit have been conducted with different resistance values and capacitance values. The results of such simulations are illustrated in Figure 11 and Table 1. Here, in the case of the frame frequency 75Hz and 1600X1200 UXGA, one line time is 1/ (75X1200), i. e., approximately ll. lu. sec. It is doubled in the case of the divided driving. Thus, one line time is assumed to be 22.21sec. As shown in Figure 11 and Table 1, when the capacitance of the panel's data line is 127pF, the tracking errors within the range of 2mV are shown at the final line time in any cases. Thus, the conditions for displaying 256 gray-scale, which require the tracking error not greater than 5mV, are satisfied.

<Table 1> Tracking Error Panel Load Conditions IVin-Vpixel 127pF, 5kg2 1. 5mV 127pF, 10m 0.7mV 127pF, 15kQ 0. 8mV 255pF, 10kQ 0. 5mV 255pF, 2oak2 1. 5mV 255pF, 30kQ 313mV

The foregoing embodiments of the present invention are merely exemplary and are not to be construed as limiting the present invention. Many alternatives,

modifications and variations will be apparent to those skilled in the art.

INDUSTRIAL APPLICABILITY As explained above, the high-gain low-power operation amplifier for driving a flat display according to a preferred embodiment of the present invention has the following strengths. The operation amplifier of a prior art ordinarily adopts the common source structure to implement the high gray-scale. Thus, the quiescent current increases. On the other hand, so as to implement the low-power operation amplifier according to a prior art, the source follower is used and thus the open circuit voltage gain decreases. Accordingly, the high gray-scale is difficult to implement in the conventional operation amplifier of a prior art. In contrast, the operation amplifier for driving a flat display according to a preferred embodiment of the present invention uses a phase splitter and a buffer having two PMOSs (or two NMOSs) and thus the high open circuit voltage gain may be obtained. Accordingly, the high gray-scale may be implemented. Furthermore, through the Class B driving, the quiescent current at the buffer unit is decreased. Therefore, the low power may be implemented at the same time.