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Title:
HIGH-LEVEL SYNTHESIS-BASED LOCK-IN AMPLIFICATION PROCESSING METHOD, SYSTEM AND APPARATUS, AND MEDIUM
Document Type and Number:
WIPO Patent Application WO/2024/051035
Kind Code:
A1
Abstract:
The present invention provides a high-level synthesis-based lock-in amplification processing method, system and apparatus, and a medium. The method comprises the following steps: determining a target circuit, and obtaining and determining a lock-in amplification function in the target circuit; describing the lock-in amplification function by means of a high-level language to obtain a first function description; verifying the accuracy of the first function description, and according to the verification result, performing high-level synthesis induction on the first function description by means of a low-level language to obtain a second function description; and performing field programmable logic gate array simulation verification according to the second function description, and outputting and obtaining a simulation verification result of the lock-in amplification function. According to the method, a high-level synthesis tool can be controlled to enable same-frequency and frequency-multiplied signals to be in one time step, so as to meet the period accuracy. Moreover, the data bit width and filter configurations of a lock-in amplification algorithm can be quickly changed, lock-in amplification algorithms with different requirements can be quickly generated, so that the development efficiency is further improved, and the method can be widely applied to the technical field of circuit simulation.

Inventors:
WANG ZIXIN (CN)
ZHANG SHIJIE (CN)
ZHANG BOWEN (CN)
LI DALIN (CN)
CHEN DIHU (CN)
KUANG ZHIJIAN (CN)
LIU JIAYE (CN)
Application Number:
PCT/CN2022/142011
Publication Date:
March 14, 2024
Filing Date:
December 26, 2022
Export Citation:
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Assignee:
UNIV SUN YAT SEN (CN)
GUANGZHOU SINE SCIENT INSTRUMENT CO LTD (CN)
International Classes:
G06F30/331
Foreign References:
CN106775905A2017-05-31
CN113779499A2021-12-10
CN106374918A2017-02-01
CN113743042A2021-12-03
US20120233578A12012-09-13
Other References:
HUANG KAN; ZHANG XIBIN; CHEN DIHU; CAI ZHIGANG; WANG ZIXIN; WANG MIN: "Implementation of Digital Lock-in Amplifier Based on High-level Synthesis", 2019 IEEE 4TH INTERNATIONAL CONFERENCE ON SIGNAL AND IMAGE PROCESSING (ICSIP), IEEE, 19 July 2019 (2019-07-19), pages 474 - 479, XP033634254, DOI: 10.1109/SIPROCESS.2019.8868834
Attorney, Agent or Firm:
JIAQUAN IP LAW (CN)
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