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Title:
HIGH-PERFORMANCE TRENCH CAPACITORS FOR DRAM CELLS
Document Type and Number:
WIPO Patent Application WO1986003333
Kind Code:
A3
Abstract:
A trench version of a high-capacitance (Hi-C) capacitor for a dynamic random-access-memory (DRAM) cell is made utilizing a modified version of the doping technique described in U.S. Pat. No. 4,471,524 and 4,472,212. A shallow highly doped trench region is thereby formed. At the same time, selected lateral surface portions of the structure are also thereby highly doped. These surface portions permit a direct electrical connection to be easily made between the capacitor and a subsequently formed adjacent access transistor.

Inventors:
LEBOWITZ JOSEPH (US)
LYNCH WILLIAM THOMAS (US)
Application Number:
PCT/US1985/002234
Publication Date:
July 17, 1986
Filing Date:
November 11, 1985
Export Citation:
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Assignee:
AMERICAN TELEPHONE & TELEGRAPH (US)
International Classes:
H01L27/04; G11C11/34; G11C11/403; H01L21/225; H01L21/822; H01L21/8242; H01L27/10; H01L27/108; H01L29/94; (IPC1-7): H01L21/225; H01L29/94
Domestic Patent References:
WO1981003241A11981-11-12
WO1985004760A11985-10-24
Foreign References:
EP0088451A11983-09-14
EP0009910A11980-04-16
Other References:
Japanese Journal of Applied Physics - Supplements, 1983, Tokyo (US) T. MORIE et al.: "Depletion Trench Capacitor Cell", pages 253-256, see figure 1
IBM Technical Disclosure Bulletin, Volume 26, No. 2, July 1983, New York (US) N.C.C. LU: "Groovetrench MIS Capacitor", pages 489-490 see the whole article
International Electron Devices Meeting, 1983, IEEE, New York (US) K. MINEGISHI et al.: "A Submicron CMOS Megabit Level Dynamic RAM Technology using Doped Face Trench Capacitor Cell", pages 319-322, see figure 1
International Electron Devices Meeting, 1983, IEEE, New York (US) E. KINSBRON et al.: "Source and Drain Junctions by Oxodizing Arsenic Doped Polysilicon", pages 674-677, see page 675, column 1, paragraphs 1,2; figures 1,2
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