Technical Field [2] This invention relates to time-to-digital conversion ("TDC"), more specifically to time to digital conversion methods and apparatus which use a differential delay between frequency-mismatched oscillators to measure time between events to high resolution. The invention has particular application in measuring jitter characteristics in high frequency digital signals. Specific embodiments of the invention are useful for on board self testing of timing circuits such as phase-locked loops ("PLLs"), delay- locked loops ("DLLs"), and serialiser/deserializers.

Another aspect of the invention relates to a finely tunable digital ring oscillator suitable for use in TDC systems according to the invention.

Background of the Invention [3] Jitter is an important characteristic of high-speed digital signals generally. While there exist sophisticated stand-alone devices capable of measuring jitter in high- speed digital signals, such devices tend to be extremely complicated and expensive. Jitter testing typically requires a long test time. Further, where the signal to be tested is internal to an integrated circuit, it may not be practical to use a stand-alone device to test for jitter.

[4] Timing circuits such as phase-locked loops, delay- locked loops, and serializers/deserializers are used widely in many high-speed integrated circuits. These circuits are used in many applications. Some examples are synthesizing clock signals, recovering data, realigning clock edges and timing the transmission of data.

[5] Jitter in the outputs of such timing circuits can cause malfunctions. These malfunctions can be very difficult to diagnose. As complex System on Chip ("SOC") integrated circuits become even more complicated and clock speeds increase into the gigahertz range, it becomes increasingly costly and time consuming to test such circuits.

[6] The definition of jitter varies depending on the field of application. In sequential circuits, e. g. CPUs, jitter is defined as the variation of the clock period, known as"cycle-to-cycle"or"period jitter". Such variation is best modelled as a frequency modulation of the clock signal. More formally period jitter can be expressed as : where VFM is the clock signal, To is the average clock period, TJ (t) is the frequency modulating jitter signal, and sgn [x] is the sign function : As shown in Figure 1A, period jitter samples are collected by measuring the duration of each period of the signal IN1.

[7] For both period and accumulative jitter measurements, M jitter samples are collected to calculate jitter characteristics, such as rms, peak-to-peak, or frequency components. For example, the rms jitter may be obtained by performing the following computations : [8] The important jitter specifications for PLLs used in digital communication interfaces are intrinsic jitter, jitter tolerance and jitter transfer. These specifications are given in standards for each application (e. g., see Bell Research Laboratories SONET transport systems : Common criteria network element architectural features GR-253 core, Issue 1, pp. 5-81, December, 1994 for SONET interfaces).

[9] Intrinsic jitter is defined as the jitter at the output of the PLL when the input is jitter-free. This is often expressed in terms of unit interval UI, which is defined as the period of a signal with a frequency equal to the average frequency of the original signal. For example in a 155. 54 MHz SONET network application, 1 UI is 6. 429 ns.

[10] Jitter transfer is defined as the ratio of the output jitter to input jitter of the PLL as a function of frequency.

[11] Jitter tolerance is the peak-to-peak amplitude of the sinusoidal jitter applied to the input of the PLL which causes 1dB power penalty (in terms of bit error rate).

[12] There is a need for systems capable of measuring jitter characteristics of high-speed digital signals.

There is a particular need for such systems capable of measuring jitter in timing circuits internal to complicated integrated circuits.

[13] Functional testing is typically the only practical way to test today's high-speed timing circuits. Most structural test methods are too intrusive (i. e. the testing itself has a significant effect on the performance of the circuit) or provide poor correlation to important specifications such as jitter. Jitter specifications are typically the single most important set of specifications for a high-speed timing circuit.

Jitter specifications include intrinsic jitter, jitter transfer functions and jitter tolerance. Testing such a circuit to determine whether its actual jitter characteristics meet its specifications is a significant problem.

[14] Various authors have proposed methods for testing devices such as PLLs. All of these proposed methods have disadvantages. R. J. A. Harvey et al. Test evaluation for complex mixed-signal IC's by introducing layout dependent faults, IEEE Colloquium on Mixed Signal VLSI Test, pp.

6/1-8, 1993 suggests testing PLLs by performing partial specification testing by measuring lock range, lock time and power supply current. Dalmia et al. Power supply current monitoring techniques for testing PLLs Proc. of Asian Test Symposium, pp. 366-371, 1997 and Dalmia et al., U. S. patent No. 5, 835, 501 disclose the use of power supply current monitoring for PLL testing.

[15] Devarayanadurg et al. Hierarchy based statistical fault simulation of mixed signal IC's Int. Test Conf. pp.

521-527, 1996 and Goteti et al. DFT for embedded charge-

pump PLL systems incorporating IEEE 1149. 1, Proc. of Custom Integrated Circuits Conf. pp. 210-213, 1997 propose methods for efficient fault simulation of PLLs and suggest lock frequency range measurement for PLL testing.

[16] Although a combination of these techniques seems to provide a good efficient fault simulation it is difficult to correlate the test results to important jitter specifications. This is partly because simulating jitter for fault-free and faulty circuits is extremely difficult due to a lack of tools capable of simulating noise in non-linear dynamic circuits.

[17] Azias et al. A unified digital test technique for PLLs using reconfigurable VCO Proc. of Int. Mixed Signal Test Workshop, 1999 discloses a reconfiguration technique for testing ring oscillator-based PLLs. This technique has the advantage of being compatible with digital test methods, but it requires reconfiguring sensitive parts of a PLL. Also, it exhibits the problem of unknown correlation of test results and functional specifications.

[18] S. Sunter et al. BIST for phase-locked loops in digital applications, Proc. of Int. Test Conf. pp. 532- 540, 1999 discloses a BIST circuit capable of measuring lock range and loop gain of a PLL in addition to performing a jitter test. Methods which use this circuit to measure jitter depend on bit error rate (BER) and so can only provide statistical information about jitter.

Such methods may give pessimistic estimates of jitter in noisy digital environments. This might lead to discarding some good devices. The jitter testing approach of Sunter et al. is limited primarily to clock recovery PLLs.

[19] US patent Nos. 5, 663, 991 and 5, 889, 435 disclose on-chip jitter measurement techniques for testing PLL circuits. The BIST circuits proposed in these patents are mixed-signal and their resolution is limited to one gate delay. This is inadequate for testing high-speed PLLs.

[20] Veillette et al. On-chip measurement of the jitter transfer function of charge-pump phase locked loops, Int.

Test Conf. pp. 776-785, 1997 disclose a jitter transfer function measurement circuit. This circuit does not have sufficient resolution for intrinsic jitter testing.

[21] Veillette et al., Stimulus generation for built in self test of charge pumped phase locked loops, Int. Test Conf. pp. 698-707, 1998 proposes a method for generating jitter at the input of a PLL for jitter transfer testing.

This method, however, requires reconfiguration of the feedback in the PLL loop, which could affect the performance of the loop.

[22] Another on-chip jitter test method is to determine jitter by measuring time intervals between the significant edges of one or two signals. Such measurement can be done with a time-to-digital converter (TDC). A TDC produces a digital output representing the time elapsed between two temporally separated events. Figures 1A, 1B and 1C illustrate respectively how period, accumulative jitter, and relative jitter can be measured through the use of a TDC 10.

[23] Various TDC circuits have been used in physics experiments. It has been suggested that such TDC circuits could be used in jitter measurement. Existing TDC circuits are, however, mixed-signal, require custom design and layout, occupy large areas, do not provide

high resolution, or rely heavily on matching of the elements.

[24] Kelkar et al. U. S. patent No. 5, 663, 991 discloses the use of a controlled delay line in an on-chip jitter measurement method. This circuit is mixed-signal and suffers from the same limitations as most TDCs.

[25] In serial communication applications, jitter can be defined as the short-term variations of a digital signal's significant instants, e. g. rising edges, from their ideal position in time. Such jitter is often denoted as"accumulative jitter"and is described as a phase modulation of a clock signal. In a clock synthesis circuit, where the absolute jitter is important, often a jitter-free (practically low-jitter) reference signal is used for jitter measurement. In such a case, the difference between the position of corresponding edges of the signal (IN1) relative to the reference clock (REF) indicates the jitter. Figure 1B illustrates how accumulative jitter samples, li (i) for i=l,..., N can be collected using a TDC.

[26] Sometimes, the relative jitter between two signals is of interest if neither of the two signals is a jitter-free signal, e. g. in data recovery circuits. Fig.

1C shows how relative jitter between the edges of signal IN1 and IN2 can be measured using a TDC.

[27] A classic method of measuring a time interval is to start a counter at the beginning of the interval and stop it when the interval ends. The resulting number in the counter will be proportional to the time interval. The resolution in this method is the period of the clock controlling the counter. To measure intrinsic jitter of a high-speed PLL (e. g. a 155MHz clock synthesis PLL), where a high resolution in the range of 20 ps is required, a

clock frequency of 50 GHZ would be needed. This method is not suitable for on-chip applications where the maximum clock available is in the range of a few hundreds of MHz.

[28] Santos, A CMOS delay locked and sub-nanosecond time-to-digital converter chip, IEEE trans on nuclear science, vol. 43, pp. 1717-1719, June, 1996 discloses a TDC based on the use of a delay chain. In this circuit, the output of the delay elements in the delay chain are set HIGH as the START rising edge travels through them. A delay locked loop (DLL) is used to calibrate the delay elements to a known delay. Such a calibration requires very good matching between all the delay elements in both the delay chain and the DLL.

[29] Arai, A time digitizer CMOS gate array with a 250 ps time resolution, IEEE Journal of Solid-State Circuits, v. 31, pp. 212-220, February, 1996 discloses an alternative TDC in which an analog delay chain and DLL are combined. This obviates the need for element matching. In both of the schemes of Santos and Arai the DLL and the controlled delay elements are analog.

[30] A fully digital TDC could be made by eliminating the DLL and using digital gates as delay elements. The trade-off is decreased accuracy due to the quantization error associated with calibration reference inputs. The resolution Ts of such methods without time interpolation is limited to one gate delay at best. In current 0. 35 um CMOS technology, the smallest gate delay is approximately 50 ps, whereas a resolution and precision of about 20ps is required for functional testing of high-speed PLLs with 155 MHz center frequency. Also, since this delay is dependent on process variations and temperature, the resolution in such schemes is not controllable.

[31] Christiansen, An integrated high resolution CMOS timing generator based on an array of delay locked loops, IEEE Journal of Solid-State Circuits, v. 31, pp. 952-957, February, 1996 proposes the use of an array of DLLs to improve the measurement resolution. Mota et al. A high resolution time interpolator based on a delay locked loop and an RC delay line, IEEE Journal of Solid-State Circuits, v. 34, pp. 1360-1366, October, 1999 propose the use of an RC delay line to increase the measurement resolution through time interpolation. Although resolutions in the range of 25ps (rms) have been reported in these papers, the design of these circuit requires a great deal of care because of the need for a high degree of matching. Also, the design and layout of the DLL need careful attention due to the presence of significant power supply noise in large mixed-signal ICs.

[32] Kalisz et al., Field programmable gate array based time to digital converter with 200 ps resolution, IEEE Trans. on Instrumentation and Measurement, v. 46, pp. 51- 55, February, 1997 propose a differential delay technique based on using two delay chains. One chain is composed of gates (each with a delay of Tg. The other chain is made of latches (each with a delay of Tl) In this technique the time quantization step is the difference between the delay of the delay elements in the two delay chains. A difficulty with this technique is that, since gates and latches are very different structures, Tg and 1l are likely to differ significantly. This makes it difficult to achieve high resolution (in the range of 20 ps or less).

[33] All the schemes mentioned above require good matching of the elements in the delay chains to achieve good accuracy. This is difficult to achieve within an

acceptable accuracy under typical process variations. As the time interval to be measured becomes longer, more elements must be added to the delay chains, making it even more difficult to assure matching of delays in the chains. When more elements more added the elements will have to be placed further apart and more routing delay will have to be accounted for. Therefore, these schemes make it difficult to provide acceptable TDC linearity. In addition, these schemes do not lend themselves well to automatic place and route. Furthermore, the resolution is set by the process parameters on each chip and cannot be controlled or adjusted.

There is a need for a system capable of measuring directly the jitter characteristics of PLLs and other timing circuits on integrated circuit chips.

Such a system should be : compact (i. e. small in area compared to the circuit under test ("CUT")) ; simple and quick to design ; robust (i. e. resistant to process variations, temperature and power supply variations) ; provide a digital output (i. e. the system should generate one or more digital signatures which can be sent off-chip at relatively low speed, e. g. serially ; accurate (measurement accuracy must be sufficient for the test) ; capable of being calibrated (i. e. the system should be calibration-free, self-calibrating, or use readily available signals to the chip for calibration) ; and, have little or no impact on the performance of the CUT.

Summary of the Invention [34] One aspect of this invention provides a time to digital converter (TDC). The TDC comprises a timing circuit which includes first and second digital oscillators. The oscillators produce first and second clock signals respectively. The first and second oscillators have different periods. The invention uses the accurately known difference between the periods of the first and second oscillators to make high resolution time measurements. In preferred embodiments of the invention, at least one of the oscillators comprises a plurality of digitally controllable delay elements. The delay elements, when activated alter the period of the oscillator.

[35] The TDC also includes a coincidence detector connected to generate a coincidence signal when a reference point in the first clock signal has a known time relationship to a corresponding reference point on the second clock signal. In preferred embodiments of the invention the coincidence detector comprises a flip flop which is set when a rising edge of the first clock signal coincides with a corresponding rising edge of the second clock signal.

[36] A first counter is connected to count a number of cycles of the first oscillator until the coincidence detector generates the coincidence signal. The number is related to the length of an interval between starting the first oscillator and starting the second oscillator.

[37] A resolution adjustment circuit is connected to start the first and second oscillators at times separated by a known interval compare the number to a threshold and, if the number is not at least equal to a threshold

value altering the period of at least one of the oscillators by activating or deactivating one or more of the digitally controllable delay elements.

[38] In a preferred, dual resolution, embodiment the first and second oscillators are switchable between a first state wherein a difference in periods of the first and second signals is TA1 and a second state wherein a difference in periods of the first and second signals is TA2 where T2 < TA1 ; and the time to digital converter comprises a resolution switching control circuit connected to switch the timing circuit from its first state to its second state, a second counter connected to count a number of edges of the first signal between a START signal and a time when the timing circuit is switched from its first state to its second state, the first counter connected to count a number of edges of the first signal between the time when the timing circuit is switched from its first state to its second state and the time when coincidence signal is generated.

[39] Another aspect of the invention provides a time to digital converter comprising a timing circuit comprising first and second digital oscillators producing first and second clock signals respectively. The first and second oscillators are switchable between a first state wherein a difference in periods of the first and second signals is TAl and a second state wherein a difference in periods of the first and second signals is TA2 where TA2 < TA1. A resolution switching control circuit is connected to switch the timing circuit from its first state to its second state when the reference point of the first clock signal approaches the known time relationship with the reference point of the second clock signal. A coincidence detector connected to generate a coincidence signal when a reference point in the first clock signal has a known

time relationship to a corresponding reference point on the second clock signal. A first counter is connected to count a number of edges of the first clock signal between the time when the timing circuit is switched from its first state to its second state and the time when the coincidence signal is generated and a second counter is connected to count a number of edges of the first signal between a START signal and a time when the timing circuit is switched from its first state to its second state.

[40] In a preferred embodiment of the invention, the resolution switching control circuit comprises a delay element connected to provide a delayed first clock signal and a coincidence detector connected to generate a coincidence signal when a reference point in the second clock signal has a known time relationship to a corresponding reference point on the delayed first clock signal. Most preferably the delay element has a first state resulting in a first delay of the delayed first clock signal and a second state resulting in a second delay of the delayed first clock signal different from the first delay.

[41] A further embodiment of the invention provides a digital timing circuit for generating first and second digital output signals having first and second periods.

The timing circuit comprises a first ring oscillator triggered by a first control signal and generating a first clock signal ; and a second ring oscillator triggered by a second control signal and generating a second control signal. At least one of the oscillators comprises a plurality of digitally controllable delay elements. The delay elements, when activated alter the period of the oscillator. The timing circuit comprises a coincidence detector connected to generate a coincidence

signal when a reference point in the first clock signal has a known time relationship to a corresponding reference point on the second clock signal. A counter is connected to count a number, N, of cycles of the first oscillator between the first control signal and the coincidence signal. A resolution adjustment circuit connected to generate the first and second control signals at times separated by a known interval, compare the number N to a threshold Nth and, if N is not at least equal to a threshold value altering the period of at least one of the oscillators by activating or deactivating one or more of the digitally controllable delay elements.

[42] A still further aspect of the invention provides a method for producing first and second digital signals having first and second periods. The method comprises providing a pair of digital oscillators ; starting the first oscillator and starting the second oscillator a time period Td after starting the first oscillator ; counting a number N of cycles of the first oscillator until a reference point on the first signal coincides with a corresponding reference point on the second signal ; if N is not at least equal to a threshold value altering the period of at least one of the oscillators and repeating these steps until N is at least equal to the threshold value.

[43] In preferred embodiments of the invention, varying a period of at least one of the oscillators comprises changing a state of a controllable delay element.

[44] A yet further aspect of the invention provides a method for time to digital conversion comprising providing first and second digital oscillators having

periods which differ by an amount Ta wherein the first and second oscillators are switchable between a first state wherein a difference in periods of the first and second signals is Ta1 and a second state wherein a difference in periods of the first and second signals is Ta2 where Ta2' Ta1 ; starting the first oscillator upon the occurrence of a first control signal and starting the second oscillator on the occurrence of a second control signal a time Td later ; when the reference points occur within a known time delay of one another switching the oscillators to their second state ; counting a number NC of edges of the first clock signal which occur between the first control signal and a time when the oscillators are switched to their second state ; and, counting a number NF of edges of the first clock signal which occur between the time when the oscillators are switched to their second state and a time when the reference points have a known time relationship.

[45] The method may include estimating a noise floor for the first and second oscillators by acquiring a first set of the numbers NF and NC for Td having a known value Tref while the known time delay has a first value and a second set of the numbers NF and NC for Td having a known value Tref, or a known multiple of Tref, while the known time delay has a second value, averaging NF and NC for each set of measurements and computing the noise floor from the average values of NF and Nc for the two sets of measurements.

[46] Another aspect of the invention provides a frequency tunable digital ring oscillator comprising a closed signal path defined at least in part by a plurality of series connected delay elements each having an input and an output the delay elements comprising at least one digitally controllable delay element. The

digitally controllable delay element comprises a gate connected in series with the signal path and a tri-state device having an input connected to an output of the gate and a control connection connected to a control device.

[47] The tri-state device may be a tri-NOT gate or a tri-state buffer, for example.

[48] Further features and advantages of the invention are described below.

Brief Description of the Drawings [49] In figures which illustrate non-limiting embodiments of the invention : Figures 1A, 1B and 1C are schematic block diagrams which illustrate respectively how period, accumulative jitter, and relative jitter can be measured through the use of a TDC ; Figure 2 is a block diagram illustrating major components of a jitter measurement circuit according to the invention ; Figure 3 is a block diagram of a TDC circuit according to the invention ; Figure 4A is a schematic circuit diagram of a simple single resolution time quantizer according to the invention ; Figure 4B illustrates waveforms of digital signals at various locations in the time quantizer of Fig. 4A ; Figure 5A is a schematic circuit diagram of a dual resolution time quantizer according to the invention ; Figure 5B illustrates waveforms of digital signals at various locations in the time quantizer of Fig. 5A ; Figure 6A is a schematic circuit diagram of a range extender circuit ;

Figure 6B illustrates waveforms of digital signals at various locations in the range extender circuit of Fig. 6A ; Figure 7A is a schematic circuit diagram of an alternative range extender circuit ; Figure 7B illustrates waveforms of digital signals at various locations in the range extender circuit of Fig. 7A ; Figure 8 is a schematic diagram of an automatic resolution adjustment circuit ; Figure 9A is a TATB checker circuit ; Figures 9B and 9C are waveforms at locations in the circuit of Figure 9A for TA > TB and TA < TB respectively ; Figure 10A is an alternative TATB checker circuit ; Figure 10B illustrates waveforms of digital signals at various locations in the TATB checker circuit of Fig.

10A ; Figure 11A is a flow chart illustrating an exhaustive search method for tuning a pair of oscillators to have a small period difference where controllable delay elements in the oscillators have fixed steps ; Figure 11B is a flow chart illustrating a directed search method for tuning a pair of oscillators to have a small period difference where controllable delay elements in the oscillators have fixed steps ; Figure 12 is a flow chart illustrating an exhaustive search method for tuning a pair of oscillators to have a small period difference where controllable delay elements in the oscillators have incrementally varying steps ; Figure 13 is a flow chart illustrating a semi- exhaustive search method for tuning a pair of oscillators to have a small period difference where controllable delay elements in the oscillators have incrementally varying steps ;

Figure 14 is a flow chart illustrating a fast search method for tuning a pair of oscillators to have a small period difference where controllable delay elements in the oscillators have incrementally varying steps ; Figures 15A through 15E are schematic diagrams illustrating various types of load elements and their simplified models ; Figure 16 is a schematic diagram of a circuit for testing the effect of control voltage variations on time delay provided by a controllable delay element ; Figures 17A and 17B are schematic diagrams of controllable delay elements based on a multiplexer ; Figures 18A, 18B and 18C are schematic views of controllable delay elements in which a variable load is applied by the input of a tri-state device ; Figures 19A and 19B are schematic diagrams illustrating the structure of typical tri-NOT gates ; Figures 20A, 20B and 20C are schematic views of controllable delay elements having tri-state devices connected in parallel with other gates ; Figure 21 is a schematic view of a selection circuit for providing a reference interval ; Figure 22 is a schematic view of a jitter generator circuit ; Figure 23 is a schematic view of a configuration of edge sample suitable for cycle-to-cycle jitter measurement ; Figure 24A is a schematic view of a configuration of edge sample suitable for relative jitter measurement ; Figure 24B is a timing diagram illustrating significant signals in the circuit of Figure 24A ; Figure 25 is a top level diagram of various components in an example embodiment of a jitter measurement system according to the invention ;

Figure 26 is a schematic diagram of the time quantizer circuit of the jitter measurement system of Figure 25 ; Figure 27 is schematic diagram of the RETAB block of Figure 25 ; Figures 28 and 29 are schematic diagrams of 3-bit and 6-bit comparators used in the RETAB block of Figure 27 ; Figure 30 is a schematic view of a calibration interval generator circuit of the jitter measurement system of Figure 25 ; Figure 31 is a schematic view of a TATB checker circuit for the jitter measurement system of Figure 25 ; and, Figure 32 is a timing diagram for some signals present during a TATB check and resolution adjustment process.

List of Reference Numerals 20 circuit 22 time-to-digital converter 24 edge sampler 26 edge sampler controller 30, 30A time quantizer 32 resolution adjustment 30B block 34 range extender block 34A range extender circuit 34B 36 calibration circuit 38 TDC controller 40, 40A oscillators 41, 41A delay elements 40B 42 coincidence detector 43A circuit 44, 44A, flip flop 46 counter 44B

48 NAND gate 50 delay element 52 resolution control 54 delay line circuit 56, 56A flip flop 58 counter 56B 59 counter 60 multiplexer 61 delay elements 70A counters 70B 71 pulse 72 comparator 73 flip flop 74A flip flops 74B 75 gate 76A, 76B delay elements 76C, 76D 77A glitch 78A flip flops 77B 78B 79 pulse 82 resolution adjustment controller 84, 84A, TATB circuit 85, 86 flip flops 84B checker 88 counter 89 gate 90A, 90B counter 92 comparator 93, 94 flip flops 100A method 100B method 110 method 112A, 112B load 113 capacitance 112C, 112D element 112E 114 switch 115A delay elements 115B 116 multiplexer 117A delay element 119 logic gate 120 tri-state NOT-gate

122 delay element 123 NOT-gate 124 tri-NOT gate 130 circuit 132, 133 flip flop 134 K DGen state machine block 140 circuit 141 delay line 142 multiplexer 143 sequence counter 150 edge sampler circuit 151, 152 flip flop 153 delay element Description [1] In this description, a variable denoted by t refers to an instant in time, T refers to a time interval, and T refers to a time delay associated with the operation of a physical structure, such as a gate or a latch. In this description the following notation is used : tSTART-the time of the START event (typically this is the time when the START signal is set HIGH) ; stop-té time of the STOP event (typically this is the time when the STOP signal is set HIGH) ; ' 'a tSTOP-tSTART the time interval to be measured ; clkA the output signal produced by oscillator 40A ; clkB the output signal produced by oscillator 40B ; TA-the period of clkA ; TB-the period of clkB ; t, (i)- the time at which the rising edge of clkX (X=A or B) occurs ; T, TA-T, the time quantization step ; * N - a value generated by the time quantizer 30 from which Td can be determined ; MA-the output state of counter CntrA ; and,

* Me-the output state of counter CntrB.

[2] This invention provides digital circuits which are capable of measuring jitter in digital signals with high resolution. The circuits may be used to measure jitter characteristics of PLLs and may also be used to measure jitter in other signals. Figure 2 shows a digital circuit 20 according to the invention. Circuit 20 includes a high-resolution time-to-digital converter 22. TDC 22 measures the duration of a time interval Td between a start event and a stop event. In the illustrated embodiment of the invention an edge sampler 24 generates the start and stop events. The start and stop events may respectively be, for example, rising edges of START and STOP signals. Edge sampler 24 is controlled by an edge sampler controller 26.

[3] Under the control of edge sampler controller 26, edge sampler 24 selects the appropriate START and STOP edges and passes them to TDC 22. Edge sampler 24 and edge sampler controller 26 can preferably be configured for measuring various jitter specifications as described in more detail below.

[4] Figure 3 illustrates a circuitry for one embodiment of TDC 22 suitable for use in this invention. TDC 22 includes a time quantizer 30 which quantizes time with a time resolution of Ta. A resolution adjustment block 32 controls Ta to be less than a programmable threshold. A range extender block 34 extends the maximum time interval that time quantizer 30 is capable of measuring. A calibration circuit 36 is used to obtain a precise estimate of T,, with reference to a low-jitter reference clock. A TDC controller 38 controls the overall operation of TDC 22.

[5] Initially the resolution of time quantizer 30 is adjusted by resolution adjustment block 32 and time quantizer is calibrated. Then edge sampler controller 26 causes edge sampler 24 to generate START and STOP signals for a signal of interest and to pass pairs of START and STOP signals as jitter samples to time quantizer 30 for measurement. Time quantizer 30 measures values related to the intervals between the START and STOP signals. These measured values can be used to determine jitter characteristics of the signal of interest, as described below.

[6] A simple single resolution time quantizer 30A is shown in Figure 4A. Time quantizer 30 may be constructed to provide multiple, preferably two, different resolutions. Figure 5A shows a time quantizer 30B which provides coarse and fine resolutions. Referring to Figure 4A, time quantizer 30A includes a pair of oscillators 40A and 40B (generally oscillators 40). Each oscillator 40 comprises a closed signal path along which a plurality of delay elements 41 are connected in series. Oscillators 40A and 40B have slightly different periods. Time quantizer 30 uses a differential method to obtain high resolution. This reduces the need for circuit matching.

[7] The time quantizer 30A of Figure 4A comprises oscillators 40, a coincidence detector 42 (in the illustrated embodiment, coincidence detector 42 comprises a flip flop 44) and a counter 46. The resolution of time quantizer 30A is determined by Ta. The periods of oscillators 40A and 40B are set to be very slightly different so that Ta is a short time. Ta may be, for example, about 20 ps. TA is slightly larger than T.

[8] Figure illustrates waveforms involved in the operation of time quantizer 30A. Oscillators 40A and 40B

start oscillating on the rising edges of START and STOP respectively. Counter 46 starts counting on the rising edge of STOP. Coincidence detector 42 determines when reference points on the waveforms of clkA and clkB are in a known temporal relationship. In the illustrated embodiment the reference points are the rising edges of clkA and clkB. Flip flop 44 samples clkB at the rising edge of clkA. If flip flop 44 detects that clkB has a value of HIGH then flip flop 44 sets EOC-flag. Assuming that Td is larger than To, EOC_flag will be low for the first cycle of clkB. However, in each successive cycle of clkB, the rising edge of clkB gets closer to the corresponding rising edge of clkA by an amount T.

Eventually the N-th rising edge of clkB will precede the corresponding rising edge of clkA by at least the setup time of flip flop 44. When this occurs, EOC-flag changes state.

[9] When EOC_flag changes state, the value in counter 46 is preserved. In the illustrated example oscillators 40 stop oscillating and counter 46 stops counting when EOC_flag is set HIGH. The value N in counter 46 indicates the value of Td. In preferred embodiments, EOC_flag also initiates processing of data and prepares TDC 20 to measure another time interval.

[10] Preferably coincidence detector 42 is constructed to avoid logic errors which might be caused by metastable behaviour of flip flop 44. Metastable behaviour may occur if, for some value of Td, the interval between corresponding rising edges of clkA and clkB is within the metastability window of flip flop 44. Under these circumstances it may take significantly longer than T , for the output EOCDFF to switch to its HIGH state. If counter were driven directly by the EOCDFF signal output

by flip flop 44 then this could cause an unknown clock state for counter 46.

[11] In the illustrated embodiment, coincidence detector 42 comprises a triple flip flop synchronizer comprising flip flops 44, 44A and 44B. The output of flip flop 44B provides the EOCflag signal. In this embodiment, if metastable behaviour of flip flop 44 prevents EOCDFF from settling to its HIGH value after the Nth rising edge of clkB then the decision to end the measurement will be made at the N+lth rising edge of clkB. This is because the relative delay between the N+lth edges of clkA and clkB is greater than the delay between the Nth edges of clkA and clkB by Tz, which is much greater than the metastability window of flip flop 44. For example, the metastability window of flip flops in some 0. 35 um CMOS digital cell libraries is less than 0. 01 ps. Since the metastability window of flip flop 44 is typically extremely short, it will not significantly affect the precision with which jitter can be measured.

[12] It can be shown that the value N in counter 46 at the end of conversion is related to Td as follows : Nutz = Td+ TC+ TQ+ TR (4) where Tc is a constant offset time, Tis the quantization error (0<TQ<T), and TR is a random error due to intrinsic jitter of gates, flip flops and other components of TDC 20.

[13] Completing one measurement takes some time. The amount of time required for each measurement depends upon the value of Td. If the error term of Equation (4) is negligible then the time Tmea5 required for one measurement can be shown to be :

+<BR> <BR> <BR> T eas = NTA = , TA TA For example, if Tu=0, measuring an interval of 1 ns with a resolution of lOps requires a time of 200 x TA. If TA = 4 ns then the measurement time will be approximately 800 ns.

[14] Those skilled in the art will appreciate that time quantizer 30A has a limited valid measurement range. From the waveforms of Figure 4B it can be seen that if : Td were larger than TA-DTB, where D is the duty cycle of clkB, then flip flop 44 will sample a HIGH value on the second rising edge of clkA. This would signal an end of conversion prematurely. It can also be seen that if Tdis less than | TB-TAI, where TA is the time between the application of the START signal to oscillator 40A and the first rising edge of clkA being applied to flip flop 44 and IB is the time between the application of the STOP signal to oscillator 40B and the first rising edge of clkB being applied to flip flop 44 then flip flop 44 will sample a HIGH value on the first rising edge of clkB regardless of the value of Td. This is because the first rising edge of clkB will occur when clkA is still HIGH.

[15] Range extender block 34 inhibits the operation of coincidence detector 42 until time quantizer circuit 30A is in its valid measurement range. In the illustrated embodiment, a NAND gate 48 is connected between flip flop 44 and counter 46. NAND gate 48 prevents EOC_flag from being applied to preserve the value in counter 46 until range extender block 34 has generated a RE-flag signal.

[16] Range extender block 34 may take various forms. One type of range extender uses a circuit which has delay elements in an input signal path. A range extender 34A

which has this construction is shown in Figure 6A.

Another type of range extender uses a circuit which has delay elements in a clock signal path. A range extender 34B which has this construction is shown in Figure 7A.

[17] Range extender circuit 34A comprises four flip flops, two k-bit counters, a k-bit comparator, and two delay elements. Figure 6B is a waveform diagram which illustrates signals at various points in range extender circuit 34A. Counters 70A and 70B respectively count the number of rising edges of clkA and clkB. Both counters are initialized to the same value, preferably zero. Since clkA is started before clkB, after the START signal starts clkA then counter 70A will contain a value MA which is greater than the value Mg contained in counter 70B. The values of counters 70A and 70B are compared by comparator 72. The output of comparator 72 will go HIGH when MA = MB.

Ré fla is set in response to comparator 72 detecting that MA = MB- [18] As noted above, MA and MB are initialized to the same value. To prevent RE-flag from being set prematurely, circuit 43A uses a flip flop 73. Flip flop 73 prevents the RE-flag signal from being set until the first rising edge of clkA has occurred, thereby ensuring that counter 70A is ahead of counter 70B.

[19] When tA (j) tB0iv < TA then MB may become equal to MA for a short period after a rising edge of clkB and before the next rising edge of clkA arrives. This may cause comparator 72 to generate a short pulse 71. Pulses 71 become wider at successive rising edges of clkB. When pulses 71 become sufficiently wide, a pulse 71 can be sampled at the same clkA rising edge by both of flip flops 74A and 74B. When all of flip flops 74A, 74B and 73

are set then the output of AND gate 75 changes state to cause the RE-flag to be set.

[20] Since range extender circuit 34A operates asynchronously, a time diversity sampling technique is used to ensure valid sampling of the output of comparator 72. On each rising edge of clkA, counter 70A registers another count. For a short period after the rising edge of clkA, the output of counter 70A may have a transient random value. This random value, if equal to MB, may cause comparator 72 to generate a short pulse, or glitch 77A (Fig 6B) at its output. Counter 70B changes its count on the rising edges of clkB. For the same reasons, comparator 72 may generate a glitch 77B at its output shortly after a rising edge of clkB. It is desirable to prevent such glitches from prematurely setting RE_flag.

[21] Delay elements 76A and 76B delay the application of the output of comparator 72 to flip flops 74A and 74B.

The signals cmp_outl and cmp_out2 which are applied to flip flops 74A and 74B respectively are delayed by different amounts r2 and r2 + T,. Choosing a delay element 76B which causes r2 to be longer than the longest expected glitch ensures that neither of flip flops 74A or 74B will be set to HIGH as a result of such glitches.

[22] The glitch width can be expected to be about % of the interval rcLx-to-Q where rCLx-to-o is the worst-case CLK- to-Q delay for an output bit of counter 70B. This assumes that the worst case process variation of TCLK-to-Q iS less than about 1/4 rCLK-to-Q The expected worst case process variation of TCLK-to-Q may be determined by performing a monte-carlo analysis of the components of counter 70B.

[23] Both of flip flops 74A and 74B must be set before the output of AND gate 75 will change state to set

RE_flag. Delay element 76A causes flip flops 74A and 74B to sample the output of comparator 72 at different times.

As the rising edges of clkA and clkB become closer together, the pulses output by comparator 72 become longer in duration. Eventually the pulses are long enough in duration to trigger both of flip flops 74A and 74B on one rising edge of clkA. Delay element 76A is selected to provide a value of rl such that when both of flip flops 74A and 74B are triggered, tBi-tArl is within the valid range described above. For example, where range extender circuit 34A is made using a 0. 35 um CMOS process then T may be selected as follows : 1 A clkB-to-cmp-oull where TclkB-to-cmp_outl is the delay between a rising edge of clkB and a corresponding rising edge of cmpoutl and Setup is the maximum setup time for flip flop 44.

[24] It is worth noting that range extender block 34 does not affect the ultimate precision or accuracy of any measurements made since it merely ensures that the ith rising edges of clkA and clkB are close enough for measuring by time quantizer 30. Range extender block 34 does not interfere with the path of signals clkA and clkB to EOC_flag. From Figure 6B it can be seen that the range extension provided by range extender circuit 34A is as follows : k-1) T [25] Figure 7A shows an alternative range extender circuit 34B. Figure 7B shows waveforms at various points in circuit 34B for the example of Td = 2. 6 TA. The core of circuit 34B comprises k-bit counters 70A and 70B which have outputs connected to a k-bit comparator 72. The

output of comparator 72 is connected to the D inputs of flip flops 78A and 78B. Delay elements 76C and 76D are placed in the clock paths of counter 70A and flip flops 78A and 78B. These delay elements provide signals clkA1 and clkA2 which are delayed versions of clkA. Circuit 34B has the advantage that the desired values for the time delays produced by delay elements 76C and 76D do not depend on other time delays in the circuit. This feature makes range extender circuit 34B especially well adapted for field programmable gate array ("FPGA") implementations of the invention.

[26] In range extender circuit 34B, counters 70A and 70B are initialized to values which differ by 1. Preferably these counters are initialized to values of 1 and 0 respectively. Counter 70A counts rising edges of clkA2 and counter 70B counts rising edges of clkB. From Figure 7B it can be understood that the number in counter 70A remains larger than the number in counter 70B as long as tA2 (i)-tB (i) > rAl+rA2, where TA1 and #A2 are the delays produced by delay elements 76C and 76D respectively. When tA2 (i)-tB (i) < TA1+ TA2 then MA becomes equal to MB for a brief time. This causes comparator 72 to generate a pulse 79.

Pulse 79 becomes wider at subsequent rising edges of clkB. When pulse 79 is wide enough that both of flip flops 78A and 78B become set at the same time then RE_flag is set.

[27] Referring now to Figure 5, a dual threshold time quantizer 30B also has two oscillators 40. Oscillators 40A and 40B begin oscillating at the rising edges of START and STOP respectively. In time quantizer 30B, oscillator 40A includes a delay element 50 which selectively provides either a shorter delay or a longer delay depending upon the value of a control signal, CRS_flag. During a first part of a measurement cycle

delay element 50 is set to provide a longer delay. This causes Ta to have a relatively large value Tzc. During a second part of the measurement, control signal CRSflag controls delay element 50 to provide a smaller delay.

This reduces To to a smaller value TSF Preferably T,, is in the range of 5 times to 30 times greater than TSF Most preferably, TScis approximately 10 times greater than TSF.

[28] During the first part of the measurement cycle the successive rising edges of clkB approach the rising edges of clkA relatively quickly because Ta is relatively large.

When the rising edges of clkB and clkA are separated in time by a value smaller than a threshold time interval then a coarse/fine resolution control circuit 52 causes control signal CRSflag to switch delay element 50 to its low delay state. In effect, each measurement begins with a coarse resolution and switches to a fine resolution when the rising edges of clkA and clkB are becoming very close to one another.

[29] In the illustrated embodiment, resolution control circuit 52 comprises a delay line 54 which produces a version of clkA delayed by an interval trine at the clock input CLK of a flip flop 56. clkB is connected to the D input of flip flop 56. When rising edges of clkA and clkB are separated by an interval of Tfine, or less, then flip flop 56 changes state and CRS_flag is set. A first counter 58 counts the number (coARss) of cycles of clkA which occur during the first part of the measurement cycle. A second counter 59 counts the number of cycles of clkA which occur during the second part of the measurement cycle.

[30] To prevent metastable behaviour of flip flop 56 from causing indeterminate states in counters 58 and 59, resolution control circuit 52 preferably comprises flip

flops 56A and 56B. Flip flops 56, 56A and 56B together comprise a triple flip flop synchronizer as described above.

[31] It can be shown that the numbers counted by coarse counter 58 and fine counter 59 are related to Td as follows : NCO2RSETAC where Td, TCI TQ, and TR, are as described above.

[32] If the error term in Equation (8) is negligible then the time required to take one measurement is given approximately by : -T Td+ TC f,,,, T "AC-'AF, [33] For example, if TC=0, and rfine=300ps then measuring an interval of 2ns with T#C =50 ps and T#F =10 ps yields coAME=34 and NFINE==30. If TA = 4 ns then the measurement time will be approximately 256 ns. It can be seen that this is significantly shorter than the time required to take a similar measurement using the single resolution time quantizer 30A.

[34] Preferably resolution control circuit 52 is constructed to allow the value of rfine to be varied. In the illustrated embodiment, delay line 54 comprises a multiplexer 60 which permits one or more delay elements 61 to be either included or not included in the signal path of delay line 54. When delay elements 61 are included in the signal path of delay line 54, Tfine has a value rfineN. When delay elements 61 are not included in the signal path of delay line 54, trine has a smaller value eF. The ability to vary rfine permits the noise floor of

time quantizer 30B to be estimated in the manner described below.

[35] The time quantizer circuits described above rely on oscillators 40A and 40B having periods which differ by only a very small amount T. Any mismatch in the gate delays or interconnect wiring between oscillators 40A and 40B can cause a significant increase in T. The resolution and accuracy of the time quantizer are degraded if Ta increases. The mismatch could also result in Tjg > TA. This would prevent the time quantizer from functioning properly.

[36] Oscillators 40 are preferably constructed in a manner which permits Ta to be set accurately. This may be done by constructing one or both of oscillators 40 using a plurality of controllable delay elements 41A. Figure 8 shows a pair of oscillators 40 which each include a number of controllable delay elements 41A. Each controllable delay element 41A includes a control line which controls the controllable delay element to provide either a longer delay or a shorter delay. The controllable delay elements 41A are controlled digitally by a resolution adjustment controller 82 to achieve relative values for TE and TA such that Ta is less than a threshold Tth, Tth is selected to provide adequate resolution and is preferably user configurable. This threshold may be supplied to the circuit as a 16-bit digital number.

[37] The amount of delay which a controllable delay element can add is given by : SCCDE ICDE (I) S CDE (O) (10) where ra) and TcDE ( are the delays provided provided the controllable delay element when it is in its longer delay

state and its shorter delay state respectively.

Resolution adjustment controller 82 generates control signals for controllable delay elements 41A. At any time the state of controllable delay elements 41A can be represented by a pair of vectors, a = aO, 1, ... an and bo, b1,... bn where each element of the vector represents the state of one of the controllable delay elements 41A.

Resolution adjustment controller 82 searches for vectors a and b which yield an acceptable value for Ta (i. e. Ta <Tth).

[38] In the currently preferred embodiment of the invention, resolution controller 82 causes time quantizer 30 to measure (in a single resolution mode) two known time intervals Tref and 2 Tref. The time intervals may be, for example, the period of accurately known reference signals. The number of counts in counter 46 is obtained for each measurement and the numbers of counts are subtracted from one another to yield a difference N#.

Assuming that measurement errors are negligible then Na and Ta are related to one another by : ref A A [39] Since Tref is constant, a larger Na corresponds to a smaller TA. For TA to be smaller than Tlh, N, must be larger than some corresponding value Nth. Resolution adjustment controller switches controllable delay elements 41A between their states until it finds a combination in which Na < Nth. The steps implemented by resolution adjustment controller to most efficiently seek appropriate vectors a and b will depend upon how much delay can be added by each controllable delay element 41A.

[40] Oscillators 40 may be constructed so that all of controllable delay elements 41A are designed to be the same. Process variations will result in variations of the delays provided by the controllable delay elements 41A.

Preferably each controllable delay element 41A is constructed so that the nominal delay, Tstept added by each controllable delay element is less than # Tth. This can be done by choosing appropriate sizes for the components used in the controllable delay element 41A.

[41] When this construction is used, as vector a (or vector b) steps through values from 0,..., 0 to 1,..., 1 then To can be stepped in increments of # Tth, or less. As long as the initial difference between TA and TB is in the range of (-# (n-1) Tth, M (n-1) Tth) then there exist vectors a and b such that Ta < Tth- [42] On a real chip it is difficult to guarantee the uniformity of the steps because the value of Tstep varies with process variations and is affected by the states of neighbouring controllable delay elements. Assume that Tstep(1) < Tstep< Tstep(u), where Tstep(1) and Tstep(u) are the lower and upper 3s thresholds of the probability density function (PDF) of Tgp (these thresholds may be estimated by performing monte-carlo simulations of loaded ring oscillators). Then, as long as Tstep (u) < Tth, vectors a and b that satisfy the resolution requirement can generally be found if : nTstep(l) < TA0-Tb0 < nTstep(l) Where 3o values of Tstep (l) and Tstepcu) are used no more than about 1% of manufactured circuits will fail to be able to meet the desired resolution even though the values of T are not uniform as a result of process variations. Where 6# values are used then fewer than about 0. 1% of

manufactured circuits will fail to provide the desired resolution.

[43] Resolution adjustment will take the maximum time if all 2n+1 combinations of vectors a and B (each combination has a different numbers of 1's in vector a or must be tried to achieve the required resolution.

[44] If Tspd) is small relative to Tth then larger numbers of controllable delay elements 41A must be provided to ensure that a suitable value for Ta can be obtained even if To-To is initially large.

[45] Instead of making the delay provided by all of controllable delay elements 41A the same, oscillators 40 may be designed so that different controllable delay elements 41A provide different delays. Preferably the delays are related to one another in an ascending series to provide resolution adjustment steps of different sizes. Most preferably : #CDEAi = (1 + #)#CDEAi-1 where 0 < 6 < 1 is a constant and TCDEi is the delay added by an it''one of controllable delay elements of an oscillator 40. For example, an oscillator 40 constructed with a series of controllable delay elements 41A such that TCDE1 = 8 ps and =0. 5 can have its period adjusted in steps of 8 ps, 12 ps, 18 ps, 27 ps, 40. 5 ps, 60. 75 ps and so on.

[46] To guarantee that oscillators 40 can be controlled to provide a value of Ta smaller than Tth, The maximum size of the smallest step (taking into account probable process variations) should be smaller than Tth.

[47] Where oscillators 40 are constructed to permit adjustment of Ta in steps of different sizes then resolution adjustment controller may take advantage of the fact that both coarser and finer adjustment steps are available. This permits very fine resolutions (for example, resolutions on the order of 5 ps or less) to be achieved while reducing the average adjustment time. A binary search algorithm is preferably used to select vectors a and b which provide a resolution Ta < Tth.

[48] In addition to adjusting oscillators 40 to provide a desired value for Ta resolution adjustment controller 82 should check to ensure that TA > TB. A TATB checker circuit 84 may be used to perform this check. Figures 9A and 10A illustrate two alternative TATB checker circuits that may be used in practising this invention. TATB checker circuit 84A of Figure 9A is used by triggering both of oscillators 40A and 40B at the same time (i. e. Td = 0). TATB checker circuit 84A includes a pair of flip flops 85, 86 and a counter 88. As the waveforms of Figure 9B illustrate, when TA < TB, flip flop 85 samples LOW until the arising edge of clkA matches that of clkB.

This occurs after ((D-1) TA +TC)/Tz cycles of clkA.

However, flip flop 86 samples a HIGH value after TC/TA cycles of clkA. Therefore flip flop 86 is set before flip flop 85.

[49] As seen in Figure 9C, if TA < TBB the reverse occurs. Resolution adjustment controller 82 can check to ensure that TA < TB by monitoring the two flags EOCflag and ERRl-flag which are set by the outputs of flip flops 85 and 86 respectively. While the condition TA < TB is being checked, the reset lines of flip flops 85 and 86 must be inactive. This is ensured in TATB circuit checker 84A by providing an OR gate 89 controlled by resolution

adjustment controller 82. OR gate 89 maintains the reset lines of flip flops 85 and 86 LOW while a check is in progress.

[50] For TATB circuit checker 84A to function properly the integer part of ((D-1) TA +TC)/Ta must not equal the integer part of TC/Tz. Otherwise, both flags may be set in the same cycle of clkA. This requirement will generally be satisfied by typical designs. For example, in a circuit implementation in a 0. 35 um CMOS process, (D-1) TA is 1. 5 ns, maximum Tc is 0. 4 ns and maximum Ta is 0. 15 ns. In the worst case the integer part of ((D-1) TA +TC)/TS iS 12 while the integer part of TOIT, is 2.

[51] Since setup and hold times for flip flops 85 and 86 could be different, flip flops 85 and 86 might be set high simultaneously on the first or second rising edges of clkA and clkB. Such a case results in decision deadlock. The alternative TATB checker circuit 84B of Figure 10A addresses this problem but is more complicated than circuit 84A. Circuit 84A may share components with time quantizer 30. for example, flip flop 85 may be the same flip flop as flip flop 44 of Figure 4.

[52] It can be seen from the waveforms of Figure 10B that counter 70A (Fig. 6A) will count faster than counter 70B as long as TA < TE. This causes MA-ME to increase as time passes. Assuming that Td=O the initial difference between the values in counters 70A and 70B will be either 0 or 1. If this difference becomes 2 or more then it must be the case that TA < TE. TATB circuit checker 84B has a pair of counters 90A and 90B. Comparator 92 compares the values in counters 90A and 90B. Counter 90B is initialized to a value which is 2 larger than the initial

value of counter 90A. For example, counters 90B and 90A are initialized to values of 2 and 0 respectively.

[53] If the values in counters 90A and 90B become equal then comparator 92 generates a signal at its output which indicates that TA < TB. The techniques for reliably detecting when the values in counters 90A and 90B are equal which are described above in respect of range extender circuits 34A or 34B are preferably also used in TATB circuit checker 84B. In the embodiment illustrated in Figure 10A the delayed clock signals clkA1 and clkA2 from range extender circuit 34B are connected to the clock inputs of flip flops 93 and 94.

[54] TATB circuit checker 84B may share components with other circuits which are not required to operate while a TATB check is being performed. For example, counter 90A may comprise at least 3 significant bits of counter 70A of Figure 4.

[55] If controllable delay elements 41A all provide substantially the same variation in To then one method that can be implemented in resolution adjustment controller 82 for selecting vectors a and b is to perform an exhaustive search. Resolution adjustment controller may comprise a 2n-bit state machine where n is the number of controllable delay elements 41A in each of oscillators 40A and 40B. n of the state machine's output bits are connected to the n controllable delay elements of oscillator 40A and the other n output bits are connected to the n controllable delay elements of oscillator 40B.

The state machine cycles through all possible combinations of a distinct vector a with a distinct vector B (in this case, two versions of a vector a are not considered distinct unless they have the different number of 1's. For example, a=1100000 is not considered

distinct from a=1000100 because both of these vectors have two 1's in them). Figure 11A shows steps in one possible exhaustive search method 100A for selecting vectors a and b. If all distinct combinations of vectors a and b have been tried and no combination which provides an acceptable TA has been found then an error signal is generated.

[56] One disadvantage of performing an exhaustive search is that it can be unnecessarily time consuming. To reduce time, an alternative method, 100B, which is shown in Figure 11B may be used. Method 100B checks only distinct vectors a if TA < TB and checks only distinct vectors b if TA > TB. This reduces the number of combinations that must be checked.

[57] Where oscillators 40 are constructed with controllable delay elements which are designed to add different delays when activated then the exhaustive search strategy becomes less practical because it requires a much larger number of combinations of vectors a and b to be checked. Up to 22n combinations may need to be checked in the worst case. An exhaustive search can be implemented easily by providing a 2n-bit counter in resolution adjustment controller 82 as shown in Figure 12.

[58] A semi-exhaustive search can be performed with the similar hardware. The semi-exhaustive search increments either a or b, depending upon whether TA>TB or TB>TA.

Figure 13 is a flow chart which illustrates steps in a semi-exhaustive search method. In a semi-exhaustive search the maximum number of combinations tested is 2n.

[59] Figure 14 depicts steps in a fast search method 110 that may be implemented in resolution adjustment

controller 82. In method 110 if TA<TB only a is adjusted because TA must be adjusted to obtain an acceptable value for T. Similarly, if TA>TB, only b is adjusted to increase TB. Since oscillators 40A and 40B are made to be very similar to one another, TA and TB will likely be initially close to one another. Therefore, the first choice is a =0.. 0 and b=0.. 0. If Na < Nth, the lowest significant bit of a (or b) (depending on whether TA<TB or TA>T,,) is set high to increase TA (or TB) by the smallest amount possible. If the required resolution is still not achieved, the next bit of a or b is set HIGH and all other bits are set LOW. This is continued until setting the i-th bit HIGH implies that or TA (or TB) has been increased too much. Then the i-th and (i-1)-th bits are set LOW and HIGH, respectively, and the process starts over by setting the 0-th bit. To illustrate method 110, assume that TA>TB, n=6 and the required resolution is ultimately achieved for b =001001. The algorithm goes through the following sequence to find the required b : 000000, 000001, 000010, 000100, 001000, 010000, 001001.

This is in contrast with the exhaustive and semi-exhaustive searches, which go through the following sequence : 000000, 000001, 000010, 000011, 000100, 000101, 000110, 000111, 001000, 001001. As can be seen from above, the fast algorithm finds the solution in 7 steps, while the exhaustive and semi-exhaustive search each require 10 steps.

[60] Controllable delay elements 41A can take any of various forms. Some types of controllable delay element may be made with standard digital cells. A controllable delay element may comprise a logic gate having a capacitive load provided by a load element. The load element permits the capacitive load to be digitally switched to different values. Each load element comprises

a digital switch and a load. Turning on the switch increases the load applied to output of the corresponding logic gate. This results in a longer propagation delay.

Figures 15A through 15E illustrate various types of load elements and their simplified models.

[61] In designing load elements it is preferable to minimize the cell area required to provide a time difference Tdiff. It is also desirable that Tdiff should be relatively insensitive to variations in the control voltage Vctrl. If Tdiff varies with fluctuations in Vecrj then any noise in Vctrl will add jitter to oscillators 40. This will increase TR with the result that time quantizer 30 will have reduced precision.

[62] In the following description, Cgs(X), Cdg(x), Cgb(x), Cdb(x), and Csb(x) are respectively the gate-source, gate-drain, gate-bulk, drain-bulk and source-bulk capacitances of the transistor Mx, where X is a transistor identifier. Values fors If are listed in Table I for various types of load element.

[63] Figure 15A shows a voltage-controlled NMOS load element 112A. Although element 112A provides a relatively large Tdiff in a small area, Tdiff is quite sensitive to V because the equivalent capacitive loading of cell is a function of Vctrl- [64] Figure 15B shows a load element 112B in which the capacitive load is a capacitance 113. A simple model for such a load element has an ideal switch S, the switch resistance Rs, the switch drain capacitance Cd(s) = Cdb(s) + Cgd (s) the switch source capacitance Cs(s)= Csb(s) + Cgs(s), and the load capacitance CL. RS is in the range of a few tens of MQ when switch 114 is OFF and a few KQ when switch 114

is ON. As is evident in the model, the Cd(s) and Cs(s) are also loading the oscillator. Since Cdb(s), Cgd(s), Csb(s), and CgSsßare functions of Vctrl, this style of load element has a high Tdiff sensitivity to Vctrl and is therefore not preferred. Any load element having a switch connected to the oscillator node suffers from this high sensitivity characteristic.

[65] Figure 15C shows an alternative load element 112C and its simple model. In the model, Cd (s) = Cdb (5) + Cgd (s This design provides a low Tdiff sensitivity to Vtrl because when switch transistor Mg is ON, the impedance of Cd(s), Zd(s)=½#f Cs(s) # Rs. Therefore, the Cd (s) variations do not affect the total loading provided by load element 112C significantly. Note also that variation in Rsdue to does not affect the capacitive loading of the cell significantly. If the Ms area is large such that CL # Cd(s) and Zd dominates (i. e. Zd (S) << Rs) then the load variation due to Vctrl variations is not significant because : CL(con)= CLCd(s)/(CL+Cd(s)) #CL. In this case, the effect of Rs is significantly diminished, which means that the load variations for ON and OFF states of switch Ms are small. This is a disadvantage when larger load variations are required. Therefore, special attention must be paid to switch size in this design. Load element 112C has the advantage that it occupies a small area for a given load.

However, fabricating a load element 112C requires that the target technology permit fabrication of floating capacitors.

[66] Figure 15D shows a load element 112D similar to load element 112C except that a NMOS gate capacitor is used instead of a parallel-plate capacitor. In the associated model, Cg(L)= Cgs(L) + Cgd(L) and Cd=Csb (L) + Cdb (L) + Cdg(s) + Cdg (s). The sensitivity of Tdiff to variations in Vctrl

is only marginally greater than that of load element 112C. In the prototype implementation, described below a load element 112D is used because it provides 10 ps delay in an area of a single-drive NOT gate and it exhibits low sensitivity to variations in Vetrj" [67] The load element 112E of Figure 15E shows a good insensitivity to variations in Vctrl but requires more area to achieve a given delay than does load element 112D. In the model for load element 112E, Cd(L)= Cgs(L)+ Cgd(L) and Cd-Cgb (L) + Cdb (S) + Cdg (S)- [68] Table I shows values for Tdiff for the load elements of Figures 15A through 15E. The numbers in Table I are for a test configuration shown in Figure 16 in which either 1, 2, 3, 4, 5, or 6 load elements were turned on.

Table II shows values for the sensitivity of Tdiff to variations in Vetrj-

TABLE I. Tdiff for various control voltages ctrl 2.5V 2.6V 2.7V 2.8V 2.9V 3V 3.1V 3.2V 3.3V 1 24.3 25. 9 7. 4 28.9 30.2 31.5 32.8 34 35. 2 2 75.7 30.3 34.7 89 93.4 97.7 101.6 105.8 109. 5 a3154. 6 162. 9 70. 9 79. 8 87. 9 95. 9203. 7 11. 2 18. 7 4 269. 1 84 99. 1 14. 2 28. 5 42. 7 56. 2 69. 4 82. 1 5 423.8 447.5 471.5 495 518.2 540.4 561.1 581.8 601. 8 6 636.4 672.7 708.7 743.5 777.7 811.1 843.4 875.1 905.2 bl 57. 4 61. 6 65. 89 70. 2 74. 3 78. 4 32. 4 86. 5 90. 2 2 142.8 153.2 163.6 173.9 184.3 194.7 204.7 214.6 224. 3 3 250.2 268.8 287.3 306.1 324.6 342.9 361 378.9 396.4 4 387.5 417.3 446.9 476.5 506.4 535.6 564.8 593.8 622. 2 5 555 598.3 642.3 686.2 730.1 773.9 817.1 859.9 902. 5 6 771. 5 34. 7 98. 6 62. 8 020 090 150 210 280 1 34. 8 4. 8 4. 9 4. 9 4. 9 5 5 5 5 2 121.1 121.3 121.4 121.5 121.6 121.7 121.9 121.9 122.1 3 262.4 262.8 263.1 263.4 263.8 264 264.2 264.3 264.6 z4 484 484.9 485.7 486.4 486.9 487.5 488 488.4 488. 9 z5 789. 4 791 792.4 793.5 794.5 795.4 796.3 797 797. 84 6 1248 1251 1253 1255 1257 1259 1260 1262 1263 1 9.44 9.47 9.43 9.44 9.45 9.39 9.44 9.55 9.49 2 33. 19 3. 25 3. 35 3. 53 3. 59 3. 67 3. 69 3. 73 3. 8 3 73.19 73.4 73.62 73.95 74.19 74.33 74.37 74.59 74. 62 4 130.3 131.1 131.5 131.9 132.3 132.8 133.1 133.4 133. 7 5 210.6 211.7 212.5 213.2 213.9 214.6 215.2 215.7 216. 3 6 316.9 318.7 320.6 321.6 323 324 325.1 326.2 327.1 1 0.844 0.825 0.904 0.757 0.891 .938 0.952 0.791 0. 761 e2 3. 33. 27. 3. 26. 35. 16. 47. 19. 31 3 7.14 7.16 7.18 7.28 7.42 7.14 7.27 7.15 7.31 4 15.72 15.83 15.68 15.73 15.71 15.73 15.75 15.82 15.77 5 28.17 28.42 28.25 28.49 28.29 28.41 28.41 28.41 28.62 6 49.38 49.47 49.56 49.4 49.46 49.46 49.56 49.53 49. 48 Table II #Tdiff STdif Vctrl #Tdiff STdifVctrl #Tdiff STdifvctrl # Vctrl #Vctrl #Vctrl al 13. 5 1. 3 bl 40. 9 1. 5 cl 0. 308 0. 03 a2 42. 2 1. 3 b2 101. 9 1. 5 c2 1. 23 0. 03 a3 80. 2 1. 2 b3 182. 8 1. 5 c3 2. 77 0. 03

a4 141. 2 1. 2 b4 293. 4 1. 6 c4 6. 09 0. 04 a5 222. 6 1. 2 b5 434. 4 1. 3 c5 10. 55 0. 04 a6 336 1. 2 b6 636. 7 1. 64 c6 18. 35 0. 408 dl 0. 06 0. 02 el-0. 1-0. 45 d2 0. 755 0. 07 e2-0. 3-0. 3 d3 1. 78 0. 08 e3 0. 211 0. 1 d4 4. 23 0. 104 e4 0. 594 0. 124 d5 7. 1 0. 108 e5 0. 569 0. 07 d6 12. 72 0. 128 e6 0. 123 0 [69] Controllable delay elements 41A may also be based on standard digital cells. This is preferable because there are some situations where it is not possible or practical to update a digital library for fabricating an oscillator for use in the invention. Figures 17A and 17B show two controllable delay elements 115A and 115B which each use a multiplexer 116 to select between two path segments for insertion into a signal path. Such controllable delay elements are useful especially where the controllable delay element should exhibit a large delay difference between its long delay and short delay states. Process variations typically cause different multiplexers made according to the same design to exhibit significant differences in propagation delays. These process dependent variations could mask small differences in delay between the two path segments. A multiplexer- based controllable delay element is particularly useful for achieving a delay increment step of about 40 ps or more.

[70] The delay difference in the two multiplexed path segments can be achieved by providing a different number of delay elements in the two path segments, as shown in figure 17A or by loading a delay element in one path

segment differently from a corresponding gate element in the other multiplexed path segment as shown in figure 17B. The construction shown in Figure 17B is preferred where 20 ps < TCDE < 60 ps. The construction shown in Figure 17A is preferred where TCDE > 60 ps.

[71] For achieving a very small TCDE on the order of a few picoseconds, one of the controllable delay elements of Figure 18A, 18B or 18C may be used. In controllable delay element 117A of Figure 18A, a logic gate 119 is loaded by the input of a tri-state NOT-gate (tri-NOT) 120. The delay of the element increases when tri-NOT 120 is activated.

[72] Figures 19A and 19B show two typical tri-NOT gate implementation as can be found in standard cell libraries. When the tri-NOT gate of Figure 19A is inactive, the load C-+ C is floating because these capacitances are in series with large impedances (transistors M1 and M4 are in high impedance mode). When M1 and M4 are turned on, these capacitances are added to the capacitive load on the input of the tri-NOT. A similar effect occurs when a tri-NOT as shown in Figure 19B is activated. A value of TCDE of 3 ps or less may be obtained in a controllable delay element 117A made with standard 0. 35 um CMOS fabrication processes.

[73] The additional capacitative loading provided by a tri-NOT gate when it is activated is a small percentage (typically about 5% to 10%) of its total loading. A controllable delay element 117A therefore is particularly useful where a very small value of TCDE is required. As shown in Figures 18B and 18C the value of TCDE can be changed by either using a different tri-state buffer as a

load element or by adding additional load elements at the output of gate 119.

[74] Figure 20 shows a controllable delay element 122 which comprises a number of similar logic gates and tri- state gates connected in parallel. All of the gates should provide similar functions and have similar propagation delays. If they do not then logic contentions may occur at the outputs of each element. In the illustrated embodiment, a NOT gate 123 is connected in parallel with a tri-NOT gate 124. When it is inactive, the tri-NOT gate 124 contributes only an output load. NOT gate 123 provides drive current as well as load. When tri-NOT gate 124 is activated, it adds a small load to the output load and some drive current to the total drive. Depending on which of the additional load or drive current has the dominating effect the delay will increase or decrease. The delay which can be controlled by a controllable delay element 122 can be estimated by : where C ; and T are the output capacitance capacitance drive current of delay element 122 when tri-NOT 124 is inactive and Ca and I# are the additional capacitance and drive current when tri-NOT 124 is active.

[75] Delay element 122 has the disadvantage that it suffers from large process variations. However, it may be used with good results for mid range values of TCDE (in the range of, for example, 20 ps to 50 ps). Delay element 122 has the advantage that it can be implemented with devices from a digital library which includes tri-state buffers but does not include tri-NOT gates. A delay

element 122 can, for example, be implemented on a FPGA.

In many FPGA block cells the only available tri-state devices are tri-state buffers.

[76] A TDC 22 according to the invention is calibrated before it is used. Where time quantizer 30 is a single resolution quantizer (for example in a time quantizer which uses circuit 30A), the relationship between N and Td is linear. Therefore, if one knows T, and T. then it is straightforward to calculate Td from N. To estimate Tc and Ta two accurately know time intervals Tcal1 and Tcal2, which may be supplied from off-chip, are measured. The resulting numbers N1 and N2 are recorded. It can be seen that : Ncal1T# = Tcall + TC + TQ1 + TR1 and, Ncal2T# = Tcal2 + TC + TQ2 + TR2 where T., and TQ2 are quantization errors, and TR, and TR2 are random errors associated with the first and second measurements respectively. Preferably TCall and Tcal2 are chosen so that Ncall-Ncal2 > 200.

[77] Tc and Tz may be estimated using a two-point calibration, in which case TC0, the estimated value of Tc <BR> <BR> <BR> <BR> is given by:<BR> Tcal2NCal1-Tcal1cal2<BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> TC0 = (17)<BR> Nl2-Nl1<BR> cal2 calf and Tao, the estimated value of Ta is given by : <BR> <BR> <BR> cal2 call<BR> cal2 cal1<BR> TC0 = (18)<BR> <BR> <BR> <BR> <BR> Ncal2-Ncal1

[78] It can be shown that the error associated with the estimation of Ta is a random variable having a mean of zero and a variance given by : <BR> <BR> <BR> -2 <BR> +<BR> 6 6(Ncal2-Ncal1)2 + (Ncal2-Ncal1)2 (19 The error associated with the estimation of Tc is also a random variable having a mean of-T/2 and a variance given by : [79] A more accurate estimate of Tc and Tz may be estimated using an n-point calibration. For an n-point calibration, n accurately known time intervals are measured by TDC 22. These time intervals are multiples of a reference interval. An objective of n-point calibration is to limit the range of TQ variations and to therefore reduce 6tuez [80] Since a low-jitter reference clock is often available on a chip for two-point or n-point calibration, it is convenient to choose Tcal1= Tref, Tcal2= 2Tref, ..., Tcaln= nTref. A circuit 130 that allows reliable generation of KTref intervals is shown in Figure 21A. In circuit 130, when Cal=0, the Ref signal is connected to the clk inputs of flip flops 132 and 133. Since the D input of flip flop 133 is always HIGH, START is set high at the first rising edge of the Ref signal. The STOP signal always is set HIGH one Ref cycle after SP In turns HIGH. Since the KDGen state machine block 134 sets SPIn to HIGH (K-1) cycles after the rising edge of the Ref signal, A delay of K Ref cycles results between the edges of START and

STOP. The waveforms in Fig 21B illustrate the operation of circuit 130 for K=0, 1 and 2.

[81] Constant delay is generated in the path of calibration signals in this circuit. The same delay will be used in the actual measurement, except for the term ##MUX1 - ##MUX2 which represents the variation of the difference in propagation delays from 10 and I1 inputs to output in the multiplexers MUX1 and MUX2, respectively.

This is important for making absolute measurements because, if the mismatch is significant, the value estimated for Tc during calibration will not be the same as the one used in actual measurements. This would cause additional error.

[82] Therefore, the Ref signal paths to clk inputs of flip flops 132 and 133 must be matched to the IN1 and IN2 signal paths to the same inputs, respectively. This is particularly important in high resolution measurement because on-chip matching of elements to a high resolution is very difficult. Here, it is assumed that this matching is achieved, and therefore the term 4 rr, t, Xl-4 TMUX2 is negligible. This matching is not required when the calibration is being performed for making differential measurements because Tc does not affect the accuracy or precision of differential measurements.

[83] Where a double resolution time quantizer 30 is used (for example, where the time quantizer circuit 30B of Figure 5 is used) each measurement generates two numbers.

To estimate T and T#(F) system system may perform perform number MCal of measurements of known time intervals. In a preferred embodiment of the invention, the it''measurement set includes the following three measurements : 1-Td (i, 1) = Trerand, Tfine= Tfinel Therefore :

N (i,1)T#(c) + Nf(i,1)T#(f) = Td(i,1) + TC + TQ(i,1) + TR(i,1) (21) 2-Td (i, 2) = 2Tref and rfine=Tfinel. Therefore : Nc Nf(i,2)T#(f) = Td(i,2) + TC + TQ(i,2) + TR(i,2) (22) Td (i,3) = 4Tref and #fine=#fine2. Therefore : c Nf(i,3)T#(f) = Td(i,3) + TC + TQ(i,3) + tR(i,3) (23) [84] Each of these measurements is made M times and the resulting three sets of M equations are averaged over i=1, ..., Mcal to yield the following equations : N (i,1)T#(c) + Nf(i,1)##(f) = Td(i,1) + TC + TQ(i,1) + TR(i,1) (25) Nc(i,2)T#(c) + Nf(i,2)T#(f) = Td(i,2) + TC + TQ(i,2) + TR(i,2) Nc(i,3)T#(c) + Nf(i,3)T#(f) = Td(i,3) + TC + TQ(i, 3) + TR (i, 3) [85] For sufficiently large values of Mcal, TR(j) and TQ(j) average to negligible values. Choosing Td(i,1)=Tref, Td(i,2)=2Tref, and Td(i,3)=4Tref is desirable because it simplifies circuit design. Assuming that noise factors are negligible, subtracting equation (26) from (25) and equation (27) from (26) yields the following system of equations : Nc(21)T#(c) + Nf(21)T#(f) = and, Nc(31)T#(c) + Nf(31)T#(f) = 3Tref (30) where : N N-N N N-N Nc(31) = Nf(3)-Nf(1) Nf(31) = Nf(3)-Nf(1) (31) [86] Solving this system of equations provides accurate estimates for To and Tc. It is important to note that Td(i,3) is measured while Tfine=7fine2 because this assures

that the determinant of equations (29) and (30) is large enough to preserve the estimation accuracy.

[87] System 22 can be used to make various types of measurement. One jitter characteristic that can be measured is RMS jitter. RMS jitter can be defined as follows : where M is the number of samples taken and Td is the time interval measured for the i-th jitter sample.

[88] Estimating Jus ils often sufficient for jitter testing. It can be shown that an estimate of JRs is given by : <BR> <BR> <BR> <BR> <BR> <BR> T 2<BR> <BR> <BR> #RMS2 = TRMS2 + ### + #2R<BR> <BR> <BR> 12 where o2R is the total RMS internal jitter of TDC 30. Ta is known through calibration. If TDC 30 is well characterized then o2R will also be known. Therefore, an accurate estimate of RMS jitter can be obtained.

[89] The error in this estimate can be shown to be inversely proportional to M. Therefore, this error can be made to be very small by using a large value for M. M may be, for example, in excess of 500 and is preferably in the range of 1000 to 2500. In designing a TDC 30 for use in estimating RMS jitter it is more important to minimize o2R than it is to minimize Ta because the value of Ta can be determined accurately during calibration of TDC 30.

[90] The variance in internal jitter of time quantizer 30 increases with the number of cycles it takes to complete a measurement. The internal jitter in time quantizer 30 can be estimated by performing two sets of measurements after calibration using a double resolution time quantizer. A first set of measurements is taken with rfine=rfine1. The result is a set of pairs of counts NC1/and Nfl. The second set of measurements is taken with rfine=rfine2 The result is a set of pairs of counts N, 2, and Nf2. The second set of counts has the same single shot accuracy as the first set of counts. However, each measurement in the second set takes more cycles of clkA to complete because #fine2<#finel. In the second set of measurements, a larger proportion of each measurement is carried out in the fine resolution mode.

[91] Since the second set of measurements take longer to complete, the total measured RMS jitter in the second set of measurements is greater than the RMS jitter in the first set of measurements. Since the input signal is the same, the internal jitter of time quantizer 30 can be determined. If we assume that the internal jitter of time quantizer 30 appears as white noise then the internal jitter in the second set of measurements will scale with a factor a relative to the internal jitter in the second set of measurements with a given by : where N1=Ncl+Nfl and N2=NC2+Nf2. If the noise is Gaussian it is possible to achieve measurement accuracy of 0. 1 ps using this technique by choosing a large M. For example, RMS jitter in a 10 MHz signal could be measured with 0. 1 ps accuracy by taking approximately M=300, 000 samples.

[92] For testing jitter tolerance and jitter transfer characteristics of devices such as clock recovery units ("CRUs") it is necessary to supply the CRU with a signal that has a known jitter. Figure 22 shows a circuit 140 which may be used to generate a signal having known jitter characteristics. A jitter-free clock signal is supplied to circuit 140. Circuit 140 includes a delay line 141, a multiplexer 142 and a sequence counter 143.

The multiplexer connects a selected tap of delay line 141 to output J in response to a control signal from sequence counter 143. Sequence counter 143 specifies which tap is connected to output J at any clock edge. For example, if delay line 141 has 8 taps and sequence counter 143 is a three bit up/down counter then circuit 140 will generate a triangular shaped jitter signal with a maximum peak-to- peak amplitude of Tg where T. is the delay introduced by each delay element of delay line 141. By using a counter with a sequence which follows a sinusoidal pattern, circuit 140 will generate a signal having jitter which varies sinusoidally with time. Sequence counter 143 may be programmable so that circuit 140 can generate various types of jitter signal at its output J.

[93] A TDC 22 may be used on-chip to measure period jitter. A histogram approach can provide statistics of such jitter. TDC 22 can measure period jitter by causing edge sampler 24 to make a number of measurements. In each measurement the edge sample passes two consecutive rising (or falling) edges of a signal Vin being measured to time quantizer 30 as START and STOP signals. After this has been done, control circuit 26 reads the value (s) of N stored in the counter (s) of time quantizer 30, passes these values to an analysis system and commences another measurement. This can be repeated until a desired number of samples has been taken. Figure 23 shows an edge

sampler circuit that may be used in making period jitter measurements.

[94] The analysis system will typically be an external tester but may also be on chip. Where the analysis system is external then the data collected is transmitted to the analysis system through a suitable interface. For example, the chip may comprise a serial bus such as a JTAG interface or a parallel interface for moving the data off-chip. Preferably an on-chip data storage area is provided to hold the collected data while it is waiting to be delivered to the analysis system.

[95] The analysis system can form a histogram of the data and calculate variance and peak-to-peak jitter. If the analysis system receives information about the time at which each sample was taken then it can also analyze frequency components of the jitter. Thus, appropriately configured systems according to the invention may be used to conduct full jitter compliance tests.

[96] In some applications, such as serial communications it is necessary to measure jitter between corresponding edges of two different signals. For example, without loss of generality corresponding edges of two signals might be required to fall within a tight time window. Figure 24A shows an edge sampler circuit 150 that can be used to generate START and STOP signals for measuring jitter between two signals IN1 and IN2. In circuit 150, flip flop 151 samples an edge of IN1 and flip flop 152 samples an edge of IN2 which is closes to the sampled edge of IN1. A delay element 153 ensures that the output of flip flop 151 has enough time to be set before the edge of IN2 arrives. This will be the case if : tIN2 > tINI - #D2 + #q1 + #s2

where Tql is the CLK-to-Q delay of flip flop 151, 152 is the setup time of flip flop 152, and T12 is the delay introduced by delay element 153.

[97] Figure 24B is a timing diagram which shows waveforms at various points in edge sampler circuit 150 for one positive and one negative value of TJ = tIN1-tIN2- The generated START and STOP signals are passed to TDC 22 for measurement of the time displacement between them.

After a measurement is completed, flip flops 151 and 152 are reset and another measurement can be taken. While the sample and hold times of flip flops 151 and 152 affect the measured time displacements, these times are constant and affect all measurements equally. They can therefore be dealt with by calibration. Further, it is typically the fluctuation in measured values between measurements that is of interest. These fluctuations are not affected by constant offsets.

[98] Relative jitter tests can be used to perform jitter tolerance limit tests of CRUs. This can be done by applying a signal with a known jitter to the CRU and then measuring the relative jitter between this input signal and a signal output from the CRU.

[99] For production tests of CRUs it is desirable to test jitter tolerance at at least two frequencies, one frequency within the loop bandwidth of the CRU and another frequency outside the loop bandwidth of the CRU.

Example [100] A TDC according to the invention has been implemented in 0. 35 um/CMOS technology. In one embodiment the circuit occupies an area equivalent to 1200 2-input NAND gates and provides a time resolution of

approximately 4 ps (-1/5 of a gate delay in current standard 0. 35 um CMOS technology). The TDC generates a digital signature which can be read out by an inexpensive tester for further analysis to obtain the jitter characteristics of the signal being measured.

[101] Figure 25 is a top level diagram of a TDC made according to the invention. In this example embodiment of the invention uniform controllable load elements have been designed as standard cells to allow for automatic place and route. The rest of the cells used in the implementation have been taken from a standard digital cell library.

[102] The jitter measurement system of Figure 25 has the following blocks : TQ : Time Quantizer ; RE-TATB : Range extender and TA > TB condition checker ; Main Counter and DivBy2 circuit ; REEOC-sync-DFF, TQEOC-sync-DFF and ERRI-sync-DFF : RE-EOC, TQ-EOC and ERRI-flag synchronizer flip-flops ; TATB Check Delay Gen : Generates a small time delay for checking TA > TB ; and, Delay Generator : Controls the selection of the delays needed for resolution adjustments, calibration and measurement.

[103] Six different controllable load elements have been designed according to the style of Figure 15D. The transistor sizes for each of these cells are given in Table III. The forth row of table III lists the additional delay in the oscillator A or B obtained by activating the cell. These controllable load elements

allow for 288ps or 8. 5% period mismatch between clkA and clkB (this is obtained when all the controllable load elements are activated). The last row of Table III lists the area of each cell. The height of all the cells is the standard cell library height. The area of the smallest cell is equivalent to the area of a double-drive 2-input NAND gate.

TABLE III-Example Controllable Load Elements CLo CL1 CL2 CL3 CL4 CLS M. [w llm/1, um] 4 4 0. 35 0. 35 0. 35 0. 35 0. 35 0. 35 ML [w µm/1 µm] 3 6 9 13.5 18 27 0. 5 0. 5 0. 5 0. 5 0. 5 0. 5 Delay (ps) 11 23 35 50 67 101 Area (w (um x h hum) 6. 3x21 7. 9x21 9. 4x21 9. 4x21 11x21 14x21 [104] Oscillators 40A and 40B in the TQ block each have a signal path which loops through 11 NAND gates and one AND gate. Six taps for each oscillator are connected to six different controllable load elements. The outputs of oscillators 40A and 40B are directly connected to the clk and D inputs of flip flop DFFEOC. These outputs are buffered before being used in other control blocks which are less time sensitive. The output of flip flop DFF-EOC is sampled and held by another flip-flop to ensure that the end-of-conversion signal, EOC-Flag, can be observed by the control blocks operating with the system clock.

[105] In addition to START and STOP inputs, two other inputs have been reserved for applying StartCheck and StopCheck signals to oscillators A and B, respectively (see Figure 26). These inputs are used to apply a Td for the purpose of checking the condition TA > TB. Without these inputs, an additional multiplexer would be required. However, when START and STOP are applied to the

time quantizer the StartCheck and StopCheck signals must he inactive (HIGH), and vice versa. The main controller block ensures this condition using four control signals, Main-Set, rbMain, CheckSet, and rbCheck. The flip-flop TQEOC-sync-DFF is provided to synchronize the TQ-EOC signal with the system clock, SCLK, in order to avoid sampling errors by the Main-Controller block.

[106] The implementation of the RE-TATB block is essentially as described above with k = 6, TA1= 1. 2 ns and rA2 = 0. 4 ns. The flip-flop REEOC-sync-DFF synchronizes the RE-EOC signal with the system clock, SCLK. This prevents errors in sampling by the Main Controller block.

Buffers Bufl to Buf6 are not necessary and are included to perform mixed signal simulations. Figure 27 is a schematic diagram for RE-TATB while Figures 27 and 28 show the 3-bit and 6-bit comparators used in RE-TATB.

[107] A 16-bit synchronous counter is used to count the number N. As shown in Fig. 4, clkA could drive the counter's clock input directly. However, the maximum operational frequency of the 16-bit counter used in this example is 250 MHz, whereas clkA has a frequency of 350 MHz. A divide by 2 divider circuit DivBy2 divides clkA by two. Thus enables the counter to count the number of clkA edges. The state of the DivBy2 circuit recovers the lost bit due to division as follows : N= 2Ncntri6-clkDiv2 (36) where Nntrs is the state of the 16-bit counter and clkDiv2 is the state of the DivBy2 flip flop. If the frequency of clkA is so high that even the frequency of clkDiv2 is too high for the counter a 2-bit or 3-bit ripple counter could be used in place of one divider to divide the clkA frequency by 4 or 8. The overflow bit of such counter can be used as the clock for the main counter.

[108] The delay generator block generates START and STOP edges with tstop - tstart = Tref, 2Tref and (tIN2-TIN1) for [selD1, SelDO] = [01], [10], and [11] respectively. When [SelDl, SeIDO] = [00], both START and STOP are set HIGH and the StartCheck and StopCheck signals are activated to check for the condition TA > TB. This block is illustrated in Figure 30.

[109] TATB Check Delay Generator generates a delay of 1. 8 nsec between the StartCheck and StopCheck edges in the TA > TB check mode. The outputs of this block are set HIGH in other modes. A schematic of this block is shown in Figure 31.

[110] The main controller monitors the outputs of all other blocks and generates required signals for controlling the operation of the TDC. The main controller may be specified using synthesizable Very High Speed Integrated Circuit Hardware Description Language ("VHDL") code. The TDC operation starts by loading a threshold Nth serially. The serial data is read through SThre input while TestStart is HIGH. Then, the controller controls the Delay Generator while the TATB Check Delay Generator block performs resolution adjustment. After adjustment, calibration is performed and the TDC switches to measurement mode.

[111] The Main Controller controls the"TATB Check Delay Generator"and"Delay Generator"to generate appropriate signals for three different time quantization modes,'TA > TB check','Nth evaluation', and'sample measurement'.

The first two modes are used in resolution adjustment and calibration while the last mode is used after calibration to measure jitter samples.

[112] The timing diagram of Figure 31 shows the behaviour of some important signals during these three modes.

During all three modes, first MainSet, rbMain, CheckSet, and rbCheck are all set LOW for five cycles of the system clock (SCLK) to ensure both oscillators 40A and 40B are in their reset states. Consequently, in'TA > TB check' mode, rbMain and MainSet are set HIGH while rbCheck and CheckSet are set LOW. This causes START and STOP signals to be set HIGH. The time quantizer is then ready to accept StartCheck and StopCheck signals.

[113] At the next SCLK edge, rbCheck turns HIGH and two SCLK cycles after that, StartCheck and StopCheck signals are generated. When'TA > TB check'is completed, MainSet, rbMain, CheckSet, and rbCheck are all set LOW again.

[114] In'Nth evaluation'and'sample measurement'modes, after the five reset SCLK cycles, rbCheck and CheckSet are set HIGH while rbMain and MainSet are set LOW. This causes StartCheck and StopCheck signals to be set HIGH.

The time quantizer is then ready to accept START and STOP signals. At the next SCLK edge, rbMain turns HIGH and on the following SCLK edge, START and STOP signals are generated. When time quantizer operation is completed, MainSet, rbMain, CheckSet, and rbCheck are all set LOW again.

[115] In measurement mode, the Main Controller instructs the Delay Generator block to pass jitter samples to the time quantizer. Upon completion of each measurement, the data is sent off-chip serially through the DataOut output. The InputReady, MeasReady, and DataReady signals are used for handshaking between the external tester and TDC.

[116] In the foregoing disclosure, conventional elements, such as power supply connections and the like are not

specifically discussed or illustrated in the drawings.

Such elements are well known to those skilled in the art and have been omitted for clarity.

[117] Those skilled in the art will appreciate that the circuits and methods described herein have various advantages. Among these are that the invention may be practised with circuits which are entirely digital and are well adapted to being designed using conventional design tools including automatic place and route. Jitter measurements having an accuracy in the order of lOps can be attained. The digital and compact nature of this TDC circuit makes it very attractive for BIST applications for testing high-speed serial communication interfaces, e. g., clock and data recovery, timing circuits, and edge placement circuits. Since the TDC provides a very high-resolution time measurement capability, it is also suitable for use in testing digital clock recovery and clock synthesis circuits. It is also notable that oscillators 40A and 40B integrate power supply noise (which is non-random). High frequency power supply noise is effectively cancelled. If oscillators 40A and 40B are made structurally very similar to one another they will be affected in substantially the same manner by any low frequency power supply noise. Therefore, low frequency power supply noise can be effectively cancelled as well.

[118] As will be apparent to those skilled in the art in the light of the foregoing disclosure, many alterations and modifications are possible in the practice of this invention without departing from the spirit or scope thereof. For example, it will be understood from the foregoing that in systems according to various embodiments of the invention :

time delay elements may be inserted in places where their effects can be compensated for in hardware or software ; logic levels may be reversed and hardware modifications made to preserve the function of the circuits in question.

[119] Accordingly, the scope of the invention is to be construed in accordance with the substance defined by the following claims.