HIGH-SPEED LOW-NOISE DYNAMIC COMPARATOR

WIPO Patent Application WO/2019/178988

A1

Provided is a high speed, low noise dynamic comparator, comprising: an input unit, comprising input NMOS transistors (M1, M2) and input PMOS transistors (M6, M9); and a latch unit, comprising latch NMOS transistors (M4, M5) and latch PMOS transistors (M7, M8), wherein the latch NMOS transistors (M4, M5) and the latch PMOS transistors (M7, M8) are connected to form a latch structure; a pull-up unit, comprising pull-up PMOS transistors (M10, M11, M12) connected to the input NMOS transistors (M1, M2); and a substrate bootstrap voltage generating circuit for generating a substrate bootstrap voltage. By using a substrate bootstrap technology of the MOS transistor, the on-resistance of the MOS transistor is reduced, the comparator speed of the comparator is increased, and the comparator speed of the comparator is further improved. At the same time, the threshold voltage of the input transistor of the comparator is reduced, so that a transconductance of the input transistor is increased, thereby reducing the equivalent input noise of the comparator, and as the comparator common mode voltage changes, the comparative delay variation of the comparator is relatively smaller.

XU DAIGUO (CN)
HU GANGYI (CN)
LI RUZHANG (CN)
WANG JIAN'AN (CN)
CHEN GUANGBING (CN)
FU DONGBING (CN)
XU SHILIU (CN)
LIU TAO (CN)
PU JIE (CN)
FENG ZHIHUA (CN)

PCT/CN2018/096084

September 26, 2019

July 18, 2018

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NO 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECH GROUP CORPORATION (CN)

H03K5/24

CN107493093A	2017-12-19
CN102957405A	2013-03-06
CN105162441A	2015-12-16
US20100245149A1	2010-09-30
US20110267145A1	2011-11-03
US20140132437A1	2014-05-15

J.Z.M.C. PATENT AND TRADEMARK LAW OFFICE (GENERAL PARTNERSHIP) (CN)

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