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Title:
HIGH SPEED LOW POWER CONSUMPTION DYNAMIC COMPARER
Document Type and Number:
WIPO Patent Application WO/2017/049989
Kind Code:
A1
Abstract:
A high speed low power consumption dynamic comparer, comprising a latch, an AND gate, a delay unit, and an XNOR gate. The latch has first to third control terminals. Outputs of the latch pass through inverters I1 and I2 respectively to produce a first comparer output signal and a second comparer output signal. The first comparer output signal and the second comparer output signal pass through the XNOR gate to produce an output signal which is taken as an input signal of the AND gate along with a control signal clk1. An output signal of the AND gate controls the gate of the sixth NMOS transistor P10. The clk1 passes through the delay unit to produce its delay signal clk2. The clk2 is input to the third control terminal of the latch. Output signals Dp and Dn of the comparer pass through the XNOR gate (XNOR) to produce an output signal. This output signal passes through the AND gate along with the control signal clk1, thus producing a control signal of the NMOS transistor P10, thereby solving the problem of static power consumption in a traditional structure.

Inventors:
XU DAIGUO (CN)
HU GANGYI (CN)
LI RUZHANG (CN)
WANG JIAN'AN (CN)
CHEN GUANGBING (CN)
WANG YUXIN (CN)
FU DONGBING (CN)
LIU TAO (CN)
Application Number:
PCT/CN2016/089044
Publication Date:
March 30, 2017
Filing Date:
July 07, 2016
Export Citation:
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Assignee:
CHINA ELECTRONIC TECH CORP 24TH RES INST (CN)
International Classes:
H03K5/22
Foreign References:
CN105162441A2015-12-16
CN104300983A2015-01-21
CN103546127A2014-01-29
CN104124971A2014-10-29
Other References:
XU, DAIGUO ET AL.: "High-speed low- power and low- power supply voltage dynamic comparator", ELECTRONICS LETTERS, vol. 1, no. 23, 5 November 2015 (2015-11-05), pages 1914 - 1916, XP006054183, ISSN: 0013-5194
Attorney, Agent or Firm:
BEIJING YIGE INTELLECTUAL PROPERTY AGENT LTD (GENERAL PARTNERSHIP) (CN)
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