Title:
IMAGE PROCESSING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2013/088664
Kind Code:
A1
Abstract:
This image processing circuit performs, in a state with reduced power consumption, pipeline processing of image data. This image processing circuit has an image processing unit which performs pipeline processing of image data having N-bit pixel data. The image processing unit has a pipeline register (400) having upper bit flip-flop circuits (401), lower bit flip-flop circuits (402), a comparison circuit (403) which determines whether or not the input values and the output values of the upper bit flip-flop circuits (401) are the same, and a clock gating control circuit (404) which controls supply of the clock signal such that, when the aforementioned input and output values are the same, the clock signal is not supplied to the upper bit flip-flop circuits (401). The pipeline register (400) does not have a circuit for controlling supply of the clock signal to the lower 1-bit flip-flop circuits (402), and holds pixel data or calculation results during pipeline processing.
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Inventors:
HOSHINO MASASHI
HARADA MASAAKI
HARADA MASAAKI
Application Number:
PCT/JP2012/007711
Publication Date:
June 20, 2013
Filing Date:
November 30, 2012
Export Citation:
Assignee:
PANASONIC CORP (JP)
International Classes:
G06T1/20; G06T1/60
Foreign References:
| JPH07262002A | 1995-10-13 | |||
| JPH05189990A | 1993-07-30 | |||
| JP2009187075A | 2009-08-20 | |||
| JP2005078518A | 2005-03-24 | |||
| JP2006345278A | 2006-12-21 |
Attorney, Agent or Firm:
WASHIDA, KIMIHITO (JP)
Koichi Washida (JP)
Koichi Washida (JP)
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Claims: