CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of priority of U.S. Provisional Patent Application No. 63/404, 642 filed September 8, 2022, the entire contents of which is hereby incorporated by reference.

TECHNICAL FIELD

The disclosure relates to an image sensor system. The disclosure further relates to an electronic device employing such an image sensor system and to a method for operating an image sensor.

RELATED APPLICATIONS

This patent application claims the priority of U.S. provisional patent application 63/404, 642, the disclosure content of which is hereby incorporated by reference.

BACKGROUND

In applications such as augmented reality (AR) , virtual reality (VR) , robotics, and computer vision, CMOS Image Sensor (CIS) cameras are used to monitor the surrounding environment. The images taken by CIS cameras are postprocessed to track objects in the environment. In addition to object detection, the algorithms may also track the motion of objects in the scene. The tracking of motion involves estimating position, velocity and acceleration of the objects. The object motion tracking mechanism involves estimating the position, velocity and acceleration of the obj ects computed from images/videos taken of the scene . In conventional implementations , data outputs of CIS cameras , i . e . , images and videos , are fed into complex Al assisted algorithms to identi fy and track obj ects . The conventional systems require high power consumption and multiple external hardware and software components .

SUMMARY OF INVENTION

The present disclosure provides an improved imaging concept that allows a more ef ficient generation of velocity and acceleration data in an image sensor .

The improved imaging concept is based on the idea of , instead of calculating velocity and acceleration based on full images or videos on the application processor, performing a determination of velocity values and acceleration values , at the source , right on the chip of the image sensor . In particular, the improved imaging concept directly uses charge values stored on capacitors located within each of the individual pixels with a speci fic sampling and read-out scheme , which are processed by a computation block located within the image sensor . For example , charge values and signals derived thereof of four or more subsequent integration periods are used to calculate a velocity value based on a time-weighted di f ference of these signals . Similarly, an acceleration value is determined based on a time-weighted di f ference of these velocity values . In other words , the velocity values and the acceleration values are each determined by numerical derivation of respective signals in the at least four subsequent integration periods for each pixel . Hence , not only regular pixel values like in a conventional image sensor but also derivative values like the velocity and acceleration values can be provided concurrently for each pixel of the image sensor at its output . The improved imaging concepts provide a solution for a true , compact , solid state , CMOS imaging sensor with simultaneous outputs of image data, velocity map image data, and acceleration map image data using the same read-out circuitry and a pipeline for all the three data streams . The improved imaging concept allows for high-speed, low-power operation, as the calculation of velocity and acceleration maps is done at pixel level eliminating the need for software post processing to calculate velocity and acceleration from captured image/video streams . The simultaneous capture of image data, velocity map data and acceleration map data from the same image sensor allows users to simpli fy their systems and allow them to quickly identi fy and track obj ects within a scene . Post processing steps , which are needed in conventional image sensors , can therefore be eliminated .

An implementation of an image sensor system according to the improved imaging concept comprises a pixel array with a plurality of pixels . Each of the pixels comprises a photodiode , a pixel buf fer and a trans fer gate coupled between the photodiode and an input of the pixel buf fer . Further elements could be included in each of the pixels .

The image sensor system comprises , for each of the pixels , an associated sampling bank . Each sampling bank comprises a first signal sampling stage connected to an output of the respective pixel buf fer, a second signal sampling stage connected in cascade with the first signal sampling stage , a third signal sampling stage connected in cascade with the second signal sampling stage , and a fourth signal sampling stage connected in cascade with the third signal sampling stage .

The image sensor system further comprises a control block that is configured to control sampling, read-out and digiti zing for all pixels of the pixel array . The control block is configured to , for each of the pixels , ef fect sampling of charges collected by the photodiode during a first integration period at least onto the fourth signal sampling stage , ef fect sampling of charges collected by the photodiode during a second integration period following, e . g . subsequently following, the first integration period at least onto the third signal sampling stage , ef fect sampling of charges collected by the photodiode during a third integration period following, e . g . subsequently following, the second integration period at least onto the second signal sampling stage , and ef fect sampling of charges collected by the photodiode during a fourth integration period following, e . g . subsequently following, the third integration period onto the first signal sampling stage .

The control block is further configured to , for each of the pixels , ef fect read-out and digiti zing of a first signal value from the fourth signal sampling stage , of a second signal value from the third signal sampling stage , of a third signal value from the second signal sampling stage and of a fourth signal value from the first signal sampling stage . For example , an analog-to-digital-converter , ADC, is employed for digiti zing . In various implementations several pixels may share a common ADC, such that a number of ADCs employed in the image sensor system is smaller than the number of pixels . In some implementations , a separate ADC may be provided for each pixel .

The image sensor system further comprises a computation block that is configured to , for each of the pixels , determine at least one derivative pixel value based on a di f ference between at least two values selected from the first signal value , the second signal value , the third signal value and the fourth signal value , and on a duration of at least one of first integration period, the second integration period, the third integration period and the fourth integration period .

In various implementations , for determining the at least one derivative pixel value , the computation block is configured to , for each of the pixels , a first pixel velocity value based on a di f ference between the first signal value and a second signal value and on a duration of the second integration period . Similarly, the computation block is configured to determine a second pixel velocity value based on a di f ference between the third signal value and a fourth signal value and on a duration of the fourth integration period . The computation block is further configured to , for each of the pixels , determine a pixel acceleration value based on a di f ference between the second pixel velocity value and a first pixel velocity value and on a duration of the second integration period, the third integration period and the fourth integration period .

The sampling bank may be a signal sampling bank .

In various implementations the image sensor system further comprises , for each of the pixels , an associated further sampling bank, which may be a reset sampling bank in which only the reset signal is stored to ensure full correlated double sampling of the read signal . Each further sampling bank comprises a first reset sampling stage connected to the output of the respective pixel buf fer, a second reset sampling stage connected in cascade with the first reset sampling stage , a third reset sampling stage connected in cascade with the second reset sampling stage , and a fourth reset sampling stage connected in cascade with the third reset sampling stage .

The control block is further configured to , for each of the pixels , ef fect sampling of a first reset level state associated with the first integration period at least onto the fourth reset sampling stage , ef fect sampling of a second reset level state associated with the second integration period at least onto the third reset sampling stage , ef fect sampling of a third reset level state associated with the third integration period at least onto the second reset sampling stage , and ef fect sampling of a fourth reset level state associated with the fourth integration period onto the first reset sampling stage . The control block is further configured to , for each of the pixels , ef fect the read-out and digiti zing of the first signal value from the fourth signal sampling stage and the fourth reset sampling stage , of the second signal value from the third signal sampling stage and the third reset sampling stage , of the third signal value from the second signal sampling stage and the second reset sampling stage , and of the fourth signal value from the first signal sampling stage and the first reset sampling stage .

For example , the further sampling bank allows to perform correlated double sampling, CDS , which allows to increase the signal quality of the pixels or the image sensor, for example with respect to PVT variations.

For example, the outputs of the sampling bank respectively signal sampling bank and the further sampling bank respectively reset sampling bank are coupled to a first and a second input of a differential ADC. Hence, each of the first, the second, the third and the fourth signal values are based on the difference between a signal level and a reset level as soon as entering the digital domain.

If the further sampling bank respectively reset sampling bank is not present in the image sensor system, a differential double sampling, DDS, can be performed, e.g. by providing a predetermined reset level signal to the ADC when digitizing the first, the second, the third and the fourth signal value. Such predetermined reset level signal may still be variable during operation of the image sensor system. For example, the reset level signal may be determined using calibration during operation, before operation or other well-known methods.

In various implementations the image sensor system may further comprise an output block being configured to provide, for each of the pixels, an output pixel signal based on at least one of the first signal value, the second signal value, the third signal value and the fourth signal value, a velocity signal based on at least one of the first pixel velocity value and a second pixel velocity value, and an acceleration signal based on the pixel acceleration value.

For example, the output pixel signal is based on a combination, e.g. a sum, of the first signal value, the second signal value, the third signal value and the fourth signal value.

For example, the velocity signal may be selected from one of the first pixel velocity value and a second pixel velocity value or may be based on a combination, e.g. a weighted sum or average of the first pixel velocity value and a second pixel velocity value.

In various implementations the image sensor system is configured to be selectively operated, e.g., based on a user input, in a standard operating mode and in at least one of a velocity operating mode and a pixel operating mode. Herein, in a standard operating mode the output block is configured to provide the output pixel signal, the velocity signal and the acceleration signal. In the velocity operating mode, the output block is configured to provide the output pixel signal and the velocity signal, e.g. without providing the acceleration signal. In the pixel operating mode, the output block is configured to provide the output pixel signal, in particular only the output signal, e.g. without the velocity signal and the acceleration signal.

Depending on the selected operating mode, determination of the excluded signal types, e.g. acceleration signal and/or velocity signal, may be suspended, such that useless operation of the computation block can be avoided and power can be saved. The computation block or the output block may still determine the output pixel signal, which is present in each of the possible operating modes.

An image sensor system according to one of the implementations described above or elsewhere in this disclosure may be employed in a camera system that is included in an electronic device , for example . For example , such an electronic device may be used in the field of AR/VR, robotics and computer vision, to name only a few .

The improved imaging concept is not limited to the apparatusbased implementations but can also be implemented with a corresponding operating method .

For example , a method for operating an image sensor according to the improved imaging concept is provided . Herein the image sensor is implemented according to one of the example implementations described above . The method comprises , for each of the pixels ,

- sampling of charges collected by the photodiode during a first integration period at least onto the fourth signal sampling stage ;

- sampling of charges collected by the photodiode during a second integration period following the first integration period at least onto the third signal sampling stage ;

- sampling of charges collected by the photodiode during a third integration period following the second integration period at least onto the second signal sampling stage ;

- sampling of charges collected by the photodiode during a fourth integration period following the third integration period onto the first second signal sampling stage ;

- reading out and digiti zing of a first signal value from the fourth signal sampling stage , of a second signal value from the third signal sampling stage , of a third signal value from the second signal sampling stage , and of a fourth signal value from the first signal sampling stage ; and

- determining at least one derivative pixel value based on a di f ference between at least two values selected from the first signal value , the second signal value , the third signal value and the fourth signal value , and on a duration of at least one of first integration period, the second integration period, the third integration period and the fourth integration period .

In various implementations determining the at least one derivative pixel value comprises

- determining a first pixel velocity value based on a di f ference between the first signal value and the second signal value and on a duration of the second integration period;

- determining a second pixel velocity value based on a di f ference between the third signal value and the fourth signal value and on a duration of the fourth integration period; and

- determining a pixel acceleration value based on a di f ference between the second pixel velocity value and the first pixel velocity value and on a duration of the second integration period, the third integration period and the fourth integration period .

In various implementations the method further comprises

- outputting an output pixel signal based on at least one of the first signal value , the second signal value , the third signal value and the fourth signal value ;

- selectively outputting a velocity signal based on at least one of the first pixel velocity value and the second pixel velocity value ; and

- selectively outputting an acceleration signal based on the pixel acceleration value . Further implementations of the operating method become readily apparent for the skilled reader from the description of the various implementations of the image sensor system above . For example , the method may be implemented in an image sensor system as described above .

BRIEF DESCRIPTION OF DRAWINGS

The improved imaging concept will be explained in more detail in the following with the aid of the drawings . Elements and functional blocks having the same or similar function bear the same reference numerals throughout the drawings . Hence their description is not necessarily repeated in the following drawings .

In the drawings :

Figure 1 shows an example implementation of an image sensor system;

Figure 2 shows a detail of an example implementation of an image sensor system;

Figure 3 shows an example timing diagram for the image sensor system in Fig . 2 ;

Figure 4 shows a detail of a further example implementation of an image sensor system;

Figure 5 shows an example timing diagram for the image sensor system in Fig . 4 ; Figure 6 shows an example representation of charge stores in the image sensor system in Fig . 4 ;

Figure 7 shows an example block diagram of an example implementation of an image sensor system;

Figure 8 shows an example implementation of wafers for an image sensor system;

Figure 9 shows an example implementation of a sampling bank;

Figure 10 shows an example implementation of an electronic device ; and

Figure 11 shows a block diagram of an example implementation of a method for operating an image sensor system .

DETAILED DESCRIPTION

Figure 1 shows an example implementation of an image sensor system comprising a pixel array 100 with a plurality of pixels 101 , 102 , ..., l On . The image sensor system further comprises , for each of the pixels 101 , 102 , ..., l On, an associated sampling bank 201 , 202 , ..., 20n, wherein each sampling bank 201 , 202 , ..., 20n comprises a first , a second, a third and a fourth signal sampling stage that are connected in cascade with each other, wherein the first signal sampling stage is connected to the corresponding pixel or a pixel buf fer of the respective pixel .

For example , sampling bank 201 comprises the first signal sampling stage 211 that is connected to an output of pixel 101 , a second signal sampling stage 212 connected in cascade with the first signal sampling stage 211, a third signal sampling stage 213 connected in cascade with the second signal sampling stage 212, and a fourth signal sampling stage 214 connected in cascade with the third signal sampling stage 213. The other sampling banks 202, ..., 20n have the same structure .

The image sensor system 10 further comprises a control block 300, a computation block 400 and an ADC 500. The ADC 500 is coupled to outputs of the sampling banks 201, 202, ..., 20n for digitizing respective signals received from the sampling banks. An output of the ADC 500 is coupled to the computation block 400.

The control block 300 is configured for controlling operation of the pixel array 100, the sampling banks 201, 202, ..., 20n, the computation block 400 and the ADC 500.

Referring now to Figure 2, a detail of an example implementation of an image sensor system, e.g. employed in the image sensor system of Figure 1, is shown. In particular, Figure 2 shows an example implementation of one of the pixels 101 in combination with the corresponding sampling bank 201 with the sampling stages 211, 212, 213, 214. The pixel 101 example is a standard 4T pixel comprising a photodiode PD, a pixel buffer SF and a transfer gate TX coupled between the photodiode PD and an input of the pixel buffer SF. The input of the pixel buffer SF corresponds for example to a floating diffusion. As should be well-known to the skilled reader, a reset circuitry with a reset transistor RST and a dual conversion gain transistor DCG and a capacitor CLG can be employed. A drain terminal of the reset transistor RST is connected to a supply potential VDD. A drain terminal of the pixel buffer SF is connected to a dedicated supply potential VDD_PIX, and a source terminal of the pixel buf fer SF is connected to a reference potential terminal VSS via a precharge transistor PC .

It should be noted that the structure of the pixel 101 is chosen as an example only and other implementations of pixels could be used as well . One common feature of such arbitrary pixel implementations is that an output of the pixel buf fer SF, respectively the source terminal of the pixel buf fer SF is connected to the sampling bank 201 respectively the first signal sampling stage 211 . A connection PS between the pixel buf fer SF and the sampling bank 201 can be used as a pixel stack connection, e . g . , for in pixel stacking, which will be described in more detail in connection with Figure 8 .

Each of the signal sampling stages 211 , 212 , 213 , 214 comprises a sample switch and a storage element . In detail , first signal sampling stage 211 comprises a first sample switch S I and a third storage element Cl . The first sample switch S I is connected to the output of the pixel buf fer SF and to a first end of the first storage element Cl . Similarly, the second signal sampling stage 212 comprises a second storage element C3 and a second sample switch S3 connected between an output of the first sample switch S I and a first terminal of the second storage element C3 . The third signal sampling stage 213 comprises a third storage element C5 and a third sample switch S5 connected between an output of the second sample switch S3 and a first terminal of the third storage element C5 . The fourth signal sampling stage 214 comprises a fourth storage element C7 and a fourth sample switch S7 connected between an output of the third sample switch S5 and a first terminal of the fourth storage element C7 and also a gate of a first read-out transistor . The respective second terminals of the storage elements Cl , C3 , C5 , C7 are connected to the reference potential terminal VSS , which also is coupled to a gate terminal of a second read-out transistor . A drain terminal of the first read-out transistor is connected to the dedicated pixel supply voltage VDD_PIX, while its source terminal is connected to a drain terminal of the second read-out transistor . A source of the second readout transistor serving an output potential V_OUT1 is coupled to the ADC 500 .

Due to the cascaded connection of the signal sampling stages 211 , 212 , 213 , 214 , the first signal sampling stage 211 is selectively operable through the first sample switch, the second signal sampling stage 212 is selectively operable through the first sample switch S I and the second sample switch S3 , the third signal sampling stage 213 is selectively operable through the first sample switch S I , the second sample switch S3 and the third sample switch S5 , and the fourth signal sampling stage 214 is selectively operable through the first sample switch S I , the second sample switch S3 , the third sample switch S5 and the fourth sample switch S7 . Referring back to Figure 1 , it should be noted that each of the pixels 101 , 102 , ..., l On comprises a photodiode RD, a pixel buf fer SF and the corresponding trans fer gate TX, and that each of the first signal sampling stages is connected to an output of the respective pixel buf fer of the corresponding pixel .

According to the improved imaging concept , the control block 300 is configured to , for each of the pixels , ef fect sampling of charges collected by the photodiode during a first integration period at least onto the fourth signal sampling stage , ef fect sampling of charges collected by the photodiode during a second integration period following the first integration period at least onto the third signal sampling stage , ef fect sampling of charges collected by the photodiode during a third integration period following the second integration period at least onto the second signal sampling stage , and ef fect sampling of charges collected by the photodiode during a fourth integration period following the third integration period onto the first signal sampling stage . This procedure is based on the ef fect that the signal sampling stages 211 , 212 , 213 , 214 are arranged in a cascaded fashion such that the last or fourth signal sampling stage 214 can only sample through the other signal sampling stages 211 , 212 and 213 , et cetera .

Referring now to Figure 3 , an example timing diagram for the image sensor system in Figure 2 is shown, wherein respective high signals correspond to a closing of the respective switches or transistors . With respect to the previously described sampling, the period between tO and tl corresponds to the first integration period, the period between tl and t2 corresponds to the second integration period, the period between t2 and t3 corresponds to the third integration period and the period between t3 and t4 corresponds to the fourth integration period .

The control block 300 is further configured to , for each of the pixels , ef fect read-out and digiti zing, e . g . via the ADC 500 , of a first signal value s i from the fourth signal sampling stage 214 , of a second signal value s2 from the third signal sampling stage 213 , of a third signal value s3 from the second signal sampling stage 212 , and of a fourth signal value s4 from the first signal sampling stage 211 . Hence, after a full sampling and read-out cycle, the first, second, third and fourth signal values si, s2, s3, s4 are present in a digital form. These signal values apparently can be used, either alone or in combination, as pixel values of pixels in the pixel array of the image sensor, similar to conventional image sensors.

Referring back to Figure 1, the computation block 400 is configured to, for each of the pixels, determine at least one derivative pixel value based on a difference between at least two values selected from the first signal value, the second signal value, the third signal value and the fourth signal value, and on a duration of at least one of first integration period, the second integration period, the third integration period and the fourth integration period.

For example, for determining the at least one derivative pixel value, the computation block 400 is configured to, for each of the pixels, determine a first pixel velocity value based on a difference between the first signal value si and the second signal value s2 and a duration of the second integration period, for example a difference between time instants t2 and tl. Similarly, the computation block is configured to, for each of the pixels, determine a second pixel velocity value based on a difference between the third signal value s3 and the fourth signal value s4 and on a duration of the fourth integration period, for example a time difference between time instant t4 and time instant t3.

The first and the second pixel velocity value, for example, are numerical derivatives of the corresponding signal values. For example, the pixel velocity values are indicative of a velocity of a changing pixel value such that they can be used for tracking an obj ect in the image represented by the pixel array .

The computation block is further configured to , for each of the pixels , determine a pixel acceleration value based on a di f ference between the second pixel velocity value and the first pixel velocity value and on the duration of the second integration period, the third integration period and the fourth integration period, for example a time di f ference between the time instant t4 and the time instant tl . Also the pixel acceleration value can be seen as a numerical derivative of the pixel velocity values or a second derivative of the signal values . Like the pixel velocity values , also the pixel acceleration value can be used for tracking obj ects in the image represented by the pixel array . Hence providing the computation block in an image sensor system according to the improved imaging concept allows for outputting velocity and acceleration images on chip in addition to normal imaging modes . This allows for high-speed acceleration and velocity images for computer vision applications , eliminating post processing steps required in conventional image sensor implementations .

It should be noted that with the example implementation as shown in Figure 2 and Figure 3 , only a single sampling bank is provided, which allows for example performing a di f ferential double sampling, DDS , e . g . by providing one or more predefined reset level signals to the ADC 500 during digiti zing . It should be noted that even with the example implementation as shown in Figure 2 also correlated double sampling, CDS , can be performed using a sampling and readout scheme as described, for example , in US patent application 17/818,962, which is incorporated herein for this purpose in its entirety.

However, the improved imaging concept is not limited to such implementation but allows CDS also by providing, for each pixel, a further sampling bank or reset sampling bank. Referring now to Figure 4, a detail of a further example implementation of an image sensor system according to the improved imaging concept is shown, which is based on the example implementation of Figure 2. In addition to the elements already explained in conjunction with Figure 2, there is additionally provided the further sampling bank 201' with corresponding first, second, third, fourth reset sampling stages 211', 212', 213' and 214', which are connected in cascade with each other, wherein the reset sampling bank 201' is connected at its input, i.e. the input of the first reset sampling stage 211', to the output of the pixel buffer SF at the pixel stack connection PS.

For example, the first reset sampling stage 211' comprises a first reset storage element C2 and a first reset sample switch S2 connected between the output of the pixel buffer SF and a first terminal of the first reset storage element. The second reset sampling stage 211' comprises a second reset storage element C4 and a second reset sample switch S4 connected between an output of the first reset sample switch S2 and a first terminal of the second reset storage element C4. The third reset sampling stage 213' comprises a third reset storage element C6 and a third reset sample switch S6 connected between an output of the second reset sample switch S4 and a first terminal of the third reset storage element C6. The fourth reset sampling stage 214' comprises a fourth reset storage element C8 and a fourth reset sample switch S8 connected between an output of the third reset sample switch S 6 and a first terminal of the fourth reset storage element C8 and to a gate of a first output transistor of the reset sampling bank 201 ' . Second terminals of the first , second, third and fourth reset storage elements C2 , C4 , C6 , C8 are commonly connected to the reference potential terminal VSS and to a gate of a second output transistor of the reset sampling bank 201 ' . Similar as for the signal sampling bank 201 , a drain terminal of the first output transistor of the reset sampling bank 201 is connected to the pixel supply voltage terminal VDD_PIX, while the source terminal of this first output transistor is connected to a drain terminal of the second output transistor of the reset sampling bank 201 ' . A source terminal of this second output transistor is coupled to the ADC 500 and provides a potential V_OUT2 .

According to the improved imaging concept , the control block 300 is further configured to , for each of the pixels , ef fect sampling of a first reset level state associated with the first integration period at least onto the fourth reset sampling stage , ef fect sampling of a second reset level state associated with the second integration period onto the third reset sampling stage , ef fect sampling of a third reset level state associated with the third integration period at least onto the second reset sampling stage , and ef fect sampling of a fourth reset level state associated with a fourth integration period onto the first reset sampling stage . A corresponding example timing diagram for full operation of the image sensor system as shown in Figure 4 is depicted in Figure 5 .

Figure 6 shows an example representation of charge stores in the image sensor system in Figure 4 , in particular indicating the amount of charges stored in the respective charge stores or storage elements Cl to C8 .

Accordingly, the ADC 500 having a first input coupled to the signal sampling bank 201 and having a second input coupled to the reset sampling bank 201 ' is configured for digiti zing of the first signal value s i , the second signal value s2 , the third signal value s3 and the fourth signal value s4 . In the various implementations described above , the first integration period, the second integration period, the third integration period and the fourth integration period may have the same duration .

In various implementations of the computation block 300 the first pixel velocity value vmapl is calculated according to and the second pixel velocity value vmap2 is calculated according to s4 — s3 vmap2 = — -

^K t4 - t3

Similarly, the pixel acceleration value amap may be calculated according to

Referring now to Figure 7 , an example block diagram of an example implementation of an image sensor system is shown . A pixel 101 , e . g . a 40 pixel as a non-limiting example , is followed by respective sample and hold capacitor banks 201 , either with or without a reset sampling bank . This structure is followed by a di f ferential ADC 500 that stores its output in a SRAM line memory 550 , which is optional and could also be integrated within the computation block 400 . An output block 600 is configured to provide the respective output signals , e . g . output pixel signals , velocity signals and acceleration signals .

In some implementations the computation of velocity and acceleration values may be performed only selectively, e . g . i f selected by a user or an application .

For example , the image sensor system 10 may be configured to be selectively operated in a standard operating mode and in at least one of a velocity operating mode and a pixel operating mode . In the standard operating mode the output block is configured to provide the output pixel signal , the velocity signal and the acceleration signal . In the velocity operating mode the output block is configured to provide the output pixel signal and the velocity signal , in particular without the acceleration signal . In the pixel operating mode the output block is configured to provide the output pixel signal , in particular without the velocity signal and the acceleration signal . Accordingly, respective computations that are not required for the requested operating mode can be omitted, thus saving power .

In various implementations of the image sensor system 10 , each of the pixels may be arranged on a first wafer, and each of the associated sampling banks , i . e . signal sampling banks and optionally reset sampling banks , is arranged on a second wafer bonded to the first wafer . This may be useful to implement in-pixel stacking . Figure 8 shows an example implementation of such arrangement with a first wafer 810 carrying the pixels 101 , 102 , ..., l On and optionally further components . The second wafer 820 being bonded to the first wafer 810 carries the associated sampling banks 201 , 202 , ..., 20n, optionally together with the respective reset sampling banks and further components like the ADC 500 and the computation block 400 . As can be seen, the respective pairs of pixels and sampling banks are respectively connected, e . g . by inter-waver connections at the respective pixel stack connection PS as shown in Figure 2 and Figure 4 . Hence an in-pixel stacking is achieved . Inpixel stacking makes a pixel level capacitor bank feasible .

For example , each of the pixels , each of the associated sampling banks , including the optional reset sampling banks , the control block and the computation block are implemented on a single chip of the image sensor system .

Figure 9 shows an example implementation of a sampling bank that can be used in any of the image sensors described above . Instead of having four sampling stages 211 , 212 , 213 , 214 , a greater number n of sampling stages being connected in cascade is provided in the sampling bank 201 , such that the last sampling stage 21n, which comprises an n-th sample switch Sn and an n-th storage element Cn, is connected to the first and the second readout transistor . Respective operation of such sampling bank should be apparent to the skilled reader from the description of the implementation shown in Figure 2 and Figure 4 above . The sampling bank with n sampling stages can also be used a further sampling bank or reset sampling bank . For example, n may be 10, without excluding smaller or greater numbers. A number n of greater than 4 can be used for additional first and second derivatives or pixel velocity and pixel acceleration values.

Considering, for example, a burst camera where we store n frames in memory, we could achieve the same effect using n storage elements like S/H capacitors within the capacitive sampling bank.

Referring now to Figure 10, an electronic device 1000 is shown which includes a camera system 1010 comprising an image sensor system 10 according to one of the implementations described in this disclosure. Such electronic device may specifically be adapted for AR, VR, robotics and/or computer vision applications.

Figure 11 shows a block diagram of an example implementation of a method for operating an image sensor system. For example, such image sensor system is implemented according to one of the examples described above. For example, in step 1101, the charges are sampled onto the sampling banks or the sampling stages. In step 1102 the sampled values are read out and digitized, e.g. using an ADC, in order to retrieve the first, second, third and fourth signal values si, s2, s3, s4 as described above.

In step 1103 a pixel velocity is determined for each pixel, as described above, e.g. by calculating a first and a second pixel velocity value. Correspondingly, in step 1104 a pixel acceleration is determined based on the previously determined pixel velocity values. In step 1105 the selected values are output depending on a selection from a user or an application . As discussed above , determination of the pixel velocity in step 1103 and/or determination of the pixel acceleration in step 1104 may be omitted i f these values are not required for the current selection or the current mode of operation . The method 1100 may start over after output of the selected values .

The embodiments of the improved imaging concept disclosed herein have been discussed for the purpose of familiari zing the reader with novel aspects of the implementation of the improved imaging concept . Although preferred embodiments have been shown and described, many changes , modi fications , equivalents and substitutions of the disclosed concepts may be made by one having skill in the art without departing from the scope of the claims .

In particular, the implementation of the improved imaging concept is not limited to the disclosed embodiments , and gives examples of many alternatives possible for the features included in the embodiments discussed . However, it is intended that any modi fications , equivalents and substitutions of the disclosed concepts be included within the scope of the claims which are appended hereto .

Features recited in separate dependent claims may be advantageously combined . Moreover, reference signs used in the claims are not limited to be construed as limiting the scope of the claims .

Furthermore , as used herein, the term "comprising" does not exclude other elements . In addition, as used herein, the article "a" is intended to include one or more than one component or element , and is not limited to be construed as meaning only one . References

FD floating di f fusion

PD photodiode

TX trans fer gate

RST reset switch

SF pixel buf fer

PS pixel stack connection

100 pixel array

101 to l On pixels

201 to 20n signal sampling bank

201 ’ to 20n ' reset sampling bank

211 to 214 , 21n sampling stage

300 control block

400 computation block

500 ADC

550 memory

600 output block

810 , 820 wafer

1000 electronic device

1010 camera system

10 image sensor system

1100 method

1101 to 1105 method steps