IMAGING DEVICE AND IMAGING DEVICE DRIVE METHOD

The invention relates to an imaging device that includes an array in which multiple pixels are arranged in the form of a matrix. BACKGROUND CMOS image sensors (Complementary Metal Oxide Semiconductor) and CCD sensors (Charge Coupled Device) are used in endoscopes, digital cameras, scanners and other electronic devices. Since they have an amplifier for each unit cell, CMOS image sensors can produce signals with a higher S/N ratio compared with CCD sensors. They also have the advantage that the power consumption can be controlled by using a CMOS logic [device] manufacturing process.

In regard to CMOS image sensors of this type, Japanese Kokai Patent Application No. 2006-217410, for example, discloses a solid-state imaging device with a wide dynamic range that includes an overflow gate that transfers overflow photoelectric charge from a photodiode to an accumulating capacitance element during an accumulation operation, and maintains high sensitivity and a high the S/N ratio.

FIG. 12 shows the configuration of one pixel of the conventional CMOS image sensor and a column output circuit that outputs a signal read from the one pixel. Pixel Pj includes a photodiode PD that performs photoelectric conversion, a transfer transistor (transfer gate) Ml connected to the photodiode, a reset transistor M2 connected to transfer transistor Ml, a source follower transistor M3, the gate of which is connected to node Nl that connects transfer transistor Ml and reset transistor M2, and a row (line) selection transistor M4 connected between source follower transistor M3 and column (rank) signal line CLj (vertical signal line). Pixel Pj comprises four transistors, and transistors Ml, M2, M3 and M4 are n-channel enhancement mode MOS transistors. Transistors Ml, M2, M3 and M4 are off during the light exposure period or charge accumulation period of photodiode PD. After completion of the charge accumulation period, gate signal Xj of transistor M4 goes high, pixel Pj is selected, and the reading of pixel Pj is started. In the figure, although one pixel Pj is shown, all the pixels on one line in the array are selected by gate signal Xj going high. When the read period starts, gate signal R of reset transistor M2 goes high, and the capacitance element having parasitic capacitance C _FD (hereinafter, floating diffusion is

abbreviated "FD") formed at node Nl is reset to the potential Vdd. After reset transistor M2 is turned off, gate signal TX of transfer transistor Ml goes high, and all the charge accumulated in photodiode PD is transferred to FD. The transferred charge is input to the gate of source follower transistor M3, and a signal in which the input voltage is amplified is produced at node N2 of column signal line CLj.

A column signal line is connected to each of the pixels in each column of the array. A constant current source I is also connected between node N2 and ground of the column signal line. The signal produced at node N2 of column signal line CLj connected to pixel Pj is accumulated in capacitor C by gate signal SH of sample-and-hold transistor M5 being set to high, and the accumulated signal is read by gate signal φ Col of column output transistor M6 being set to high. In this way, signals for one line's worth of pixels are read via the column signal line from multiple pixels arranged two-dimensionally, and the signals for one line's worth of pixels will be output in sequence to each pixel.

In order to improve the sensitivity of the CMOS image sensor, the S/N ratio of the signals read from pixels must be improved. The charge accumulated in photodiode PD can be considered as being amplified by a multistage amplifier circuit and output. Representing the multistage amplifier circuit schematically gives the configuration in FIG. 13. Noise factor F in such a multistage amplifier circuit is represented by the following formula, and if the value of F approaches 1, the noise rejection performance will improve. Formula 1: F = F ₁ +-^^ + ^^ + ^{2 ~} +. . .

G ₁ G ₁ G ₂ G ₁ G ₂ G ₃

As is evident from the formula above, to improve the S/N ratio, the gain of the initial stage should be raised. For this purpose, capacitance (C _FD ) of FD of a pixel may be made smaller, and signal voltage VF (V _FD = Q/C _FD ) of the charge accumulated in FD may be made larger. However, when capacitance C _FD of FD is made smaller, capacitance Cpo of photodiode PD must also be made correspondingly smaller. This is because all the charge accumulated in photodiode PD must be transferred to FD. The maximum amplitude of photodiode PD is about 1 V, and when capacitance Cpo of photodiode PD becomes smaller, the amount of charge accumulated in photodiode PD, namely, the number of electrons, decreases.

External light includes so-called shot noise, and when the number of electrons accumulated in photodiode PD drops below a certain constant value, the S/N ratio falls. The S/N ratio of photodiode PD can be represented by the following formula, and to suppress the effects caused by shot noise, the S/N ratio should be at least 40 dB or more.

Signal(number of electons) Formula 2: S I N = 20 Log , y] Signal(number of electons)

In this way, with a conventional CMOS image sensor, when capacitance C _FD of FD is made smaller with the intention of improving the S/N ratio (gain) to improve sensitivity, the number of electrons accumulated in photodiode PD decreases, and conversely, there is the incompatible problem of the S/N ratio dropping. An objective of the invention was to solve this trade-off problem with the objective of improving the S/N ratio and providing a high- sensitivity imaging device. SUMMARY

An imaging device in accordance with embodiments of the principles of the invention includes multiple pixels arranged in a two-dimensional array. Each pixel includes a photodiode that receives light to produce charge, a capacitance element, and a transfer transistor connected between the photodiode and the capacitance element, and the capacitance of the capacitance element is less than the capacitance of the photodiode. The drive method includes the following steps: an accumulation step to turn the transfer transistor off and accumulate charge in the photodiode isolated from the capacitance element, a first transfer step that can turn the transfer transistor on at a fixed period in a first charge transfer mode and transfer the first charge accumulated in the photodiode to the capacitance element, a step to reset the capacitance element, and a second transfer step that can turn the transfer transistor on at a fixed period in a second charge transfer mode and transfer the second charge accumulated in the photodiode to the capacitance element. The drive method additionally includes a synthesis step that synthesizes the first charge transferred in the first transfer step and the second charge transferred in the second transfer step. The drive method could additionally include a step to determine whether the first charge transferred in the first transfer step is smaller than a first threshold value, and when it is determined to be smaller than the first threshold value, the aforementioned

synthesis step would not synthesize the first charge and the second charge. The drive method could additionally include a step to determine whether the second charge transferred in the second transfer step is larger than a second threshold value, and when it is determined to be larger than the second threshold value, the aforementioned synthesis step would not synthesize the first charge and the second charge.

The drive method may additionally include a step to convert the first and second analog signals obtained by the first and second transfer steps into first and second digital signals, and the aforementioned synthesis step could synthesize the converted first and second digital signals. Preferably, a first voltage signal is applied to the gate of the transfer transistor in the first transfer step, a second voltage signal is applied to the gate of the transfer transistor in the second transfer step, and the second voltage is larger than the first voltage. Also preferably, the first transfer step, the reset step, and the second transfer step are performed during the horizontal blanking period. An imaging device in accordance the invention has multiple pixels, which are multiple pixels arranged in the form of a matrix, wherein each pixel includes a photodiode that photoelectrically converts the received light, a capacitance element having a capacitance smaller than the capacitance of the photodiode and a transfer transistor connected between the photodiode and the capacitance element, and a drive circuit that supplies a first transfer signal that turns the transfer transistor on in a first charge transfer mode and a second transfer signal that turns the transfer transistor on in a second charge transfer mode. The transfer transistor transfers the first charge accumulated in the photodiode to the capacitance element in response to the first transfer signal, and the second charge accumulated in the photodiode to the capacitance element in response to the second transfer signal. Preferably, each pixel additionally includes a reset transistor for resetting the charge of the capacitance element, and the aforementioned drive circuit additionally supplies a reset signal for resetting the transistor to the reset transistor between the first transfer signal and the second transfer signal.

Preferably, the imaging device additionally includes a column output circuit connected to each pixel via a column signal line, and the column output circuit includes a circuit that accepts the first and second signals produced on the basis of the aforementioned

transferred first and second charges via the aforementioned column signal line and synthesizes the first and second signals.

The column output circuit could also include an analog-to-digital conversion circuit that converts the first and second signals, and the aforementioned synthesizing circuit could synthesize the digitally converted first and second signals. The synthesizing circuit could also include a first accumulation circuit where the first signal is accumulated and a second accumulation circuit where the second signal is accumulated, and could synthesize the first and second signals accumulated by the first and second accumulation circuits. In this case, the first and second accumulation circuits include first and second transistors connected to the column signal line, and first and second capacitors connected to the first and second transistors, and the aforementioned drive circuit supplies first and second drive signals for driving the first and second transistors in response to the first transfer signal to the first transistor and the second transfer signals to the second transistors.

It is also possible that at least a MOS transistor to which the aforementioned capacitance element is connected not include a source or drain region produced using LDD implantation to reduce parasitic capacitance between the gate electrode and the source or drain region. In this case, the MOS transistor constituting the circuit excluding the aforementioned multiple pixels has an LDD structure.

The electronic device pertaining to the invention includes an imaging device with the aforementioned configuration, and a display device that displays signals output from the imaging device. The imaging system pertaining to the invention includes an imaging device with the aforementioned configuration and a processing device that processes signals output from the imaging device. The electronic device or imaging device is, for example, a digital camera, endoscope, display system, etc. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the schematic configuration of an embodiment of a CMOS image sensor according to an embodiment of the invention.

FIG. 2 is a conceptual view comparing an embodiment of the CMOS image sensor in accordance with the invention with the prior art. FIG. 2 at (a) is an example with a light quantity of 100%; FIG. 2 at (b) is an example with a light quantity of 70%; and, FIG. 2 at (c) is an example with a light quantity of 40%.

FIG. 3 is a schematic view showing the photodiode pixel transfer operation. FIG. 4 shows a first circuit example of a CMOS image sensor according to the invention.

FIG. 5 illustrates the operation of an example of the synthesis circuit. FIG. 6 shows a second circuit example of the CMOS image sensor according to the invention.

FIG. 7 is a timing diagram for the circuit example of FIG. 6. FIG. 8 is a schematic plan view of a four-transistor pixel.

FIG. 9 is a cross section through line A-A in FIG. 8. FIG. 9 at (a) shows the parasitic capacitance of a conventional FD, and FIG. 9 at (b) shows the parasitic capacitance according to an embodiment of the invention.

FIG. 10 illustrates a process for reducing the parasitic capacitance of floating diffusion (FD).

FIG. 11 shows other pixel configuration examples. FIG. 11 at (a) is a circuit example requiring 2.5 transistors per pixel, and FIG. 11 at (b) is a circuit example requiring three transistors per pixel.

FIG. 12 shows a circuit example for a conventional four-transistor pixel. FIG. 13 shows noise factor F in a multistage amplifier circuit. REFERENCE NUMERALS AND SYMBOLS AS SHOWN IN THE DRAWINGS In the figures, 100 represents a CMOS image sensor, 110 an array, 120 a shift register,

130 a column output circuit, 140 a timing generator, 200 an A/D converter, and 210 a synthesis circuit DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

In accordance with an aspect of the invention, when accumulated charge is transferred to the photodiode, the signal voltage can be increased by making the capacitance element of the capacitance element smaller, and the gain can be made larger. Thus, the S/N ratio and the sensitivity can be improved. On the other hand, because the capacitance of the photodiode is not made as small as the capacitance of the capacitance element, the charge accumulated in the photodiode can be kept to a fixed value, noise is suppressed, and the S/N ratio can be improved. Example embodiments of CMOS image sensors in accordance with the invention are described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the schematic configuration of an example CMOS image sensor in accordance with an embodiment of the invention. CMOS image sensor 100 comprises an array 110 with multiple pixels arranged in m rows and n columns, a shift register 120 connected to each pixel of array 110 via row selection lines Xp (p = 1, 2, ..., k, ..., m), an output circuit 130 connected to the pixels in each column of array 110 via column signal lines CLq (q = 1, 2, ..., k, ..., n), and a timing generation circuit 140 that produces various timing signals φ , φ Col, SHl, SH2, TX and R. The array and circuits are formed monolithically on a semiconductor substrate.

Shift register 120 selects row selection lines Xp in sequence from Xl to Xn based on clock signal φ supplied from timing generation circuit 140. For example, when shift register 120 drives row selection line Xj high, the n pixels connected to row selection line Xj are selected. Each pixel includes a photodiode that converts received light into charge, and when n pixels are selected by shift register 120, the charge of the n pixels is read to column output circuit 130 via column signal line CLq. Column output circuit 130 holds one line's worth of signals corresponding to the charge of the n pixels, and sequentially outputs the held n signals from output terminal OUT according to signal φ Col supplied from timing generation circuit 140.

FIG. 2 explains the concept of the CMOS image sensor of this embodiment. The circuit configuration of the pixels is essentially the same as the circuit configuration shown in FIG. 12, but in the conventional CMOS image sensor, capacitance Cpo of photodiode PD and capacitance C _FD of FD are approximately equal. In contrast, in the CMOS image sensor of this embodiment, capacitance Cpo of floating diffusion FD is less than capacitance Cpp of photodiode PD. Moreover, with respect to the drive method, with a conventional CMOS image sensor, the charge accumulated in photodiode PD is transferred one time to FD. In contrast, with the image sensor of this embodiment, the charge accumulated in photodiode PD is transferred to FD multiple times.

The case in which capacitance Cpo of the floating diffusion is about one -half of capacitance Cpo of photodiode PD and the charge accumulated in photodiode PD is transferred to FD divided into two times will be explained below and compared with a conventional CMOS image sensor.

As shown in FIG. 2 at (a), for a given pixel Pj, when photodiode PD receives a light quantity of 100%, a conventional CMOS image sensor will transfer all of charge Q accumulated in capacitance Cpo of photodiode PD to FD by turning the transfer transistor on. The transferred charge is amplified (by source follower transistor M3), and a signal with voltage V (V = Q/C _PD ) set by charge Q is obtained.

In contrast, in this embodiment, the on mode of transfer transistor Ml is set in two stages. For example, the on-resistance of transfer transistor Ml is variable since the gate voltage applied to transfer transistor Ml is varied. Therefore, in the first transfer, the transfer transistor turns on in a first transfer mode, and a charge (Ql) equal to about half of charge Q accumulated in capacitance Cpo of photodiode FD is transferred to FD, and a signal with voltage Vl set by charge Ql is obtained. Next, in the second transfer, the transfer transistor turns on in a second transfer mode, the remaining charge Q2 of charge Q accumulated in capacitance Cpo of photodiode FD is transferred to FD, and a signal with voltage V2 set by charge Q2 is obtained. By synthesizing the signal with voltage Vl and the signal with voltage V2, essentially a signal according to charge Q (Q = Ql + Q2) can be obtained. Voltage Vl and V2 increase by increasing capacitance Cpo of FD, and the gain of FD can be increased. Moreover, the reduction of charge Q accumulated in photodiode PD can be inhibited.

FIG. 2 at (b) shows a comparison of the conventional sensor and this embodiment when a light quantity of 70% is received, and FIG. 2 at (c) shows a similar comparison when a light quantity of 40% is received. As shown in FIG. 2 at (c), when a light quantity of 50% or less is received, in the first transfer, charge Ql transferred from photodiode PD to FD is essentially zero, i.e., no charge is transferred. In such cases, when a signal produced by charge Ql and a signal produced by charge Q2 are synthesized, the noise contained therein is added, regardless of whether the signal produced by charge Ql is zero, which is undesirable. Therefore, if the light quantity is less than 50%, synthesis of the signal produced by charge Ql and the signal produced by charge Q2 need not necessarily take place.

FIG. 3 is a potential diagram that schematically shows the transfer operation for the charge accumulated in photodiode PD. As shown in FIG. 3 at (a), reset transistor M2 is turned on prior to transferring charge Q accumulated in photodiode PD, and the potential of FD is reset. By resetting the potential, potential V _FD formed in FD is higher than potential V _PD of photodiode PD.

Next, as shown in FIG. 3 at (b), transfer transistor Ml is turned so that it conducts at potential V _f1 . Approximately half of the charge of photodiode PD, from 0 V to potential Vf ₁ , is transferred to FD. Next, as shown in FIG. 3 at (c), transfer transistor Ml is turned on, charge Ql accumulated in FD is read, and the charge in FD is again reset. Next, as shown in FIG. 3 at (d), transfer transistor Ml is turned on so that it conducts at potential V _f2 , which is higher than potential V _PD - Therefore, the remaining charge on photodiode PD, from potential V _f i to potential Vpo, is transferred to FD.

FIG. 4 shows a first circuit example of a CCD image sensor according to the invention. The pixel circuit configuration is the same as the four transistors in the conventional type as described above; namely, it includes transistors Ml, M2, M3 and M4. However, capacitance C _FD of FD is about one-half of capacitance C _PD of photodiode PD (C _FD ^ 1/2C _PD ). For example, the voltage of photodiode PD is about 1.5 V, Vdd = 3.3 V, capacitance C _PD = 1.2 fFd, and capacitance C _FD = 0.8 fFd.

Column output circuit 130 includes a s ample- and-hold transistor M5 connected to node N2 of column signal line CLj, an A/D converter 200 that converts analog signals sampled and held by transistor M5 into digital signals, a synthesis circuit 210 that synthesizes the digital converted signals, and an output transistor M6 that outputs the synthesized signals according to signal φCol.

As described above, when the charge accumulated in photodiode PD of pixel Pj is read after completion of the accumulation period, the charge of photodiode PD is transferred to FD divided twice. In the example shown in FIG. 4, charge Ql (Ql = 1.2 x 1.5V = 1.8 fC), for example, is transferred in the first transfer operation by transfer transistor Ml. Voltage Vl of the signal at FD will be Vl = 1.8/0.8 = 2.25 V. The signal voltage of FD is applied to the gate of source follower transistor M3, and output voltage according to this input voltage is produced at node N2 of column output line CLj. When the gate signal SH of transistor M5 goes high, the signal at node N2 is supplied to A/D converter 200, where the signal is converted to a digital signal Sl. Converted digital signal Sl is supplied to synthesis circuit 210 where it is held.

After sample-and-hold transistor M5 is turned off, reset transistor M2 is again turned on and the charge of FD is reset. Next, the second transfer operation by transfer transistor Ml

is performed, and remaining charge Q2 of photodiode PD is transferred to FD. A charge signal of FD is produced at node N2, as in the first transfer. Then the signal at node N2 is supplied to A/D converter 200 by making gate signal SH of transistor M5 high, and converted to a digital signal S2. Converted digital signal S2 is supplied to synthesis circuit 210.

Synthesis circuit 210 synthesizes digital signal Sl from the first transfer and digital signal S2 from the second transfer. The synthesized digital signal is output as a read signal for pixel Pj via transistor M6.

FIG. 5 shows a preferred operation example of synthesis circuit 210. In this figure, Sl represents the signal from the first transfer, and S2 represents the signal from the first transfer. If signal S2 > Vth ₂ , synthesis circuit 210 synthesizes a signal S from the signals from the first transfer and the second transfer (S = Sl + S2). On the other hand, if S2 < Vth2, synthesis circuit 210 does not synthesize signal Sl from the first transfer and signal S2 from the second transfer (S = S2). In this case, because the light quantity of photodiode PD is less than 50%, as shown in FIG. 2 (c), in other words, because charge Ql transferred the first time is 0, there would be more noise if signal Sl were added. In the same way, if signal Sl > V _th i, S = Sl + S2; and if signal Sl < V^ ₁ , S = S2, which is satisfactory. The aforementioned threshold value voltage Vthi can be the dark current value (the output value when there is no incident light) or a value close to the value may be used; and the aforementioned threshold voltage value V _th2 can be the value of the saturation current of signal S2 or a value close to the value may be used.

For the synthesis of digital signals S 1 and S2 above, an example performed on-chip was shown, but it could also be performed off-chip. In the latter case, the sampled and held analog signals from the first and second transfers could be output in sequence from column output circuit 130, converted to digital signals by an off-chip A/D converter, and synthesized.

A second circuit example of a CMOS image sensor according to the invention is described with reference to FIGS. 6 and 7. FIG. 6 shows the configuration of the column output circuit of a second circuit example, and FIG. 7 is its timing diagram. The second circuit example differs from the first circuit example, and the signals obtained from the first and second transfers are synthesized using analog processing.

As shown in FIG. 6, column output circuit 130 includes a clamping transistor M7 connected between node N3 and Vdd, a sample-and-hold transistor M8 connected to node N3, an output transistor M9 connected to sample-and-hold transistor M8, a capacitor Cl connected between connection node N4 of M9 and transistor M8, a sample-and-hold transistor MlO connected to node N3, an output transistor Mi l connected to sample-and- hold transistor MlO, a capacitor Cl connected between ground and node N5 connecting transistors MlO and Mi l, and a capacitor C2 connected between ground and node N6 connecting transistors M9 and Mi l. Column output circuit 130 is connected to node N2 of each column signal line CLj via a capacitor C. Light exposure (charge accumulation) of photodiode PD is performed as shown in

FIG. 7. The light exposure period can be 16.6 msec, for example. When the light exposure period is completed, shift register 120 sequentially drives the lines of the matrix high, so that the pixels for each line are selected. The pixel read period is about 10 μsec. When signals produced by a CMOS image sensor are used for image display, the pixels are read during the horizontal planking period.

Next, timing generation circuit 140 (see FIG. 1) supplies a gate signal R to reset transistor M2 via shift register 120, in order to reset FD. After timing generation circuit 140 supplies the reset signal, gate signal Cp and sample-and-hold signal SHl goes high, clamping transistor M7 and transistor M8 turns on, and capacitor Cl is reset. Next, transfer transistor Ml is turned on in the first transfer mode by timing generation circuit 140 supplying a low- voltage gate signal TX to transfer transistor Ml via shift register 120, and charge Ql of photodiode PD is transferred to FD. A signal with voltage VsI according to charge Ql is thus produced at node N2 of column signal line CLj. Next, timing generation circuit 140 drives sample-and-hold signal SHl high and transistor M8 turns on. Charge Ql according to the first transfer (Ql = Cl x VSl) thus accumulates on capacitor Cl.

When the first transfer is completed, timing generation circuit 140 supplies a gate signal R to reset transistor M2 via shift register 120, and the reset transistor M2 again turns on, resetting FD. Then, timing generation circuit 140 turns clamping transistor M7 and sample-and-hold circuit MlO on, resetting capacitor C2. Next, timing generation circuit 140 supplies a gate signal TX to transfer transistor Ml via shift register 120, transfer transistor

Ml thereby turns on in the second transfer mode, and remaining charge Q2 of photodiode PD is transferred to FD. A signal at voltage Vs2 according to charge Q2 is obtained at node N2 of column signal line CLj. When transistor Ml 1 is turned on by gate signal SH2, charge Q2 from the second transfer (Q2 = Cl x VS2) accumulates on capacitor C2. Output transistors M9 and Mil turn on when timing generation circuit 140 supplies

φ Col for the number of column signal lines to column output circuit 130, and charge Ql and charge Q2 accumulated on the two capacitors Cl are added and output as signal Vout shown in the following formula. Here, signal Vout is output during the image signal output period.

Formula 3 V = — ;t (V l + V 2)

""' 2CI + C2 ^s Next, the method for reducing capacitance C _FD of FD in this embodiment will be explained. FIG. 8 is a plan view schematically showing a four-transistor pixel, and FIG. 9 is a cross section through line A-A in FIG. 8 that is used to explain the parasitic capacitance of FD. FIG. 9 at (a) shows a conventional configuration, and FIG. 9 at (b) shows the configuration of this embodiment. In FIG. 8, the region enclosed by the solid line represents the diffusion region, and the region enclosed by the broken line represents a polysilicon gate electrode. Capacitance C _FD of FD is parasitic capacitance formed at connection node Nl of reset transistor M2 and transfer transistor Ml. In a conventional CMOS image sensor, the parasitic capacitance of FD, as shown in FIG. 9 at (a), includes wiring capacitance C _METAL of the metal wiring connecting node Nl (n ⁺ diffusion region) and the gate of source follower transistor M3, FD junction capacitance C _JC between the n ⁺ diffusion region and the p-well of FD, oxidation film capacitance Cox produced by the gate oxidation film of source follower transistor M3, and overlap capacitance C _OP between the gate electrode and the source and drain regions produced by the LDD (Lightly Doped Drain) structure of the transistor. The ratios of each parasitic capacitance are as follows: wiring capacitance C _METAL about 18%, FD junction capacitance C _JC about 8%, oxidation film capacitance Cox about 22%, and overlap capacitance C _OP about 52%. Thus, it can be seen that overlap capacitance C _OP produced by the LDD structure accounts for more than half of the total parasitic capacitance. Therefore, in this embodiment, ion implantation used to realize the LDD structure was omitted in order to reduce the overlap capacitance C _OP produced by the LDD

structure. As shown in FIG. 9 at (b), n ⁺ diffusion regions (source and drain) matched to the side wall oxide (side wall) of the polysilicon gate were formed for transistors Ml, M2 and M3, and no n ^" diffusion regions matched to the polysilicon gate were formed.

FIG. lOat (a) shows the fabrication process for a transistor with a conventional LDD structure. A gate oxide film is formed on a substrate, then a gate electrode is formed using polysilicon, ions are implanted [with] the polysilicon gate used as a mask, and an n ^" LDD region is formed. A side wall is then formed on the side wall of the polysilicon gate, and an n ⁺ active region is formed with the polysilicon gate and side walls used as a mask. In contrast, in this embodiment, as shown in FIG. 10 at (b), by skipping ion implantation for the LDD, the formation of an n ^" diffusion region that overlaps the gate electrode can be omitted.

In the embodiment explained above, the LDD structure for transistors Ml, M2 and M3 was eliminated; however, the LDD structure could also be eliminated for row selection transistor M4. And the timing generation circuit and the column output circuit except for the pixels also use an LDD structure. In the embodiment described above, four- transistor pixels were used, but naturally, the pixels can be constituted differently. FIG. 11 at (a) shows a circuit example requiring 2.5 transistors per pixel. In this example, two photodiodes PDl and PD2 share a reset transistor, a source follower transistor and a row selection transistor. FIG. 11 at (b) shows the elimination of the row selection transistor from the four-transistor pixel. In this case, reset transistor M2 is selectively connected to two values, voltage Vrst and voltage VIo. When no pixel is to be selected, voltage VIo is applied to the gate of source follower transistor M3, and the pixels in that row will not be selected.

Additionally, in the embodiment described above, an example in which the capacitance of FD was about one-half the value of the photodiode capacitance, and charge is divided and transferred twice was used; however, the ratio of the capacitance of FD to photodiode capacitance can be changed as required, as can the number of charge transfers. For example, the device could be constituted so that the capacitance of FD is about one-third of the photodiode capacitance, and charge is divided and transferred three times. In addition, it could be constituted so that the capacitance of FD is about one-quarter of the photodiode capacitance, and charge is divided and transferred four times.

The imaging device according to the invention can be used in digital cameras, portable telephones, and other electronic devices requiring imaging elements.

Those skilled in the art to which the invention relates will appreciate that the described embodiments are merely example implementations, and that many other implementations are possible within the scope of the claimed invention.