| US20140002285A1 | 2014-01-02 | |||
| US20150146832A1 | 2015-05-28 | |||
| US20060117083A1 | 2006-06-01 |
ALIREZA FASIH ET AL.: "New computational modeling for solving higher order ODE based on FPGA", 2009 2ND INTERNATIONAL WORKSHOP ON NONLINEAR DYNAMICS AND SYNCHRONIZATION, 1 September 2009 (2009-09-01)
| CLAIMS What is claimed is: 1. An improved physical analog computer having at least one integrator adapted to receive and process at least one input signal to be subjected to a forcing function, said analog computer incorporated in a physical system to be monitored, the physical system having needs, the computer comprising: a means for time-scaling said improved physical analog computer to better match analog-computational time with the needs of said physical system by introducing an input time-scaling factor to said forcing function and to the integrating operations of said at least one integrator, wherein: said time-scaling factor is greater than 1 to slow down said analog-computational time, and said time-scaling factor is less than 1 to speed up said analog-computational time; said time-scaling being digitally controlled, whereby the introduction of said time-scaling factor adjusts the computational speed of said improved physical analog computer and response times to better match the needs of said physical system. 2. The improved physical analog computer of claim 1, wherein said at least one integrator has a sinusoidal input, the at least one integrator having a unit-gain frequency having a gain magnitude, wherein said time-scaling is calibrated by ensuring that the gain magnitude of the unit-gain frequency of said at least one integrator equals 1. 3. The improved physical analog computer of claim 2, wherein said at least one integrator’s type is selected from the group consisting of active resistor-capacitor integrator and transconductor-capacitance integrator. 4. The improved physical analog computer of claim 2, wherein said time-scaling calibration is accomplished using at least one voltage-controlled resistor. 5. The improved physical analog computer of claim 2, wherein said time- scaling calibration is accomplished automatically via direct tuning. 6. The improved physical analog computer of claim 5, wherein said automatic direct tuning employs an external reference selected from the group consisting of frequency and resistance. 7. The improved physical analog computer of claim 6, wherein said time- scaling calibration uses a crystal clock to set a precise time-scaling factor. 8. The improved physical analog computer of claim 7, wherein an element to be scaled is selected from the group consisting of: a MOSFET; a parallel combination of nMOS and pMOS transistors; an array of resistors; an array of capacitors; and an amplifier with gain control, with said amplifier providing input to said at least one integrator. 9. The improved physical analog computer of claim 8, wherein the element to be time- scaled is an array of capacitors, wherein said array of capacitors is a digitally controlled, binary-weighted capacitor array. 10. The improved physical analog computer of claim 2, wherein said time-scaling calibration is accomplished automatically via indirect tuning. 11. The improved physical analog computer of claim 10, wherein said automatic indirect tuning employs an oscillator, a reference frequency, an external clock to adjust a control voltage. 12. The improved physical analog computer of claim 11, wherein said time-scaling calibration uses a crystal clock to set a precise time-scaling factor. 13. The improved physical analog computer of claim 12, wherein the element to be scaled is selected from the group consisting of: a MOSFET ; a parallel combination of nMOS and pMOS transistors; an array of resistors; an array of capacitors; and an amplifier with gain control, with said amplifier providing input to said at least one integrator. 14. The improved physical analog computer of any of claims 1 through 13, wherein said improved physical analog computer is adapted to process signals from a physical system selected from the group consisting of electrical-battery-management system, electrical-power-plant-control system, petroleum-refinery system, maritime-propulsion system, refrigeration-control system, heating-ventilation-and-air-conditioning (HVAC) system, and automobile-control system. 15. A method of operating an improved physical analog computer having at least one integrator adapted to receive and process at least one input signal to be subjected to a forcing function, said analog computer incorporated in a physical system to be monitored, the physical system having needs, the analog computer having a computation speed, the method comprising the steps of: introducing an input time-scaling factor to said improved physical analog computer to better match analog-computational time with the needs of said physical system by introducing said input time-scaling factor to said forcing function and to the integrating operations of said at least one integrator, wherein: said time-scaling factor is greater than 1 to slow down said analog-computational time, and said time-scaling factor is less than 1 to speed up said analog-computational time; said time-scaling being digitally controlled, whereby the introduction of said time-scaling factor adjusts the computational speed of said improved physical analog computer and response times to better match the needs of said physical system. 16. The method of claim 15, wherein said at least one integrator has a sinusoidal input, the at least one integrator having a unit-gain frequency having a gain magnitude, wherein said time-scaling is calibrated by ensuring that the gain magnitude of the unit-gain frequency of said at least one integrator equals 1. 17. The method of claim 16, wherein said at least one integrator’s type is selected from the group consisting of active resistor-capacitor integrator and transconductor-capacitance integrator. 18. The method of claim 16, wherein said time-scaling calibration is accomplished using at least one voltage-controlled resistor. 19. The method of claim 16, wherein said time-scaling calibration is accomplished automatically via direct tuning. 20. The method of claim 19, wherein said automatic direct tuning employs an external reference selected from the group consisting of frequency and resistance. 21. The method of claim 20, wherein said time-scaling calibration uses a crystal clock to set a precise time-scaling factor. 22. The method of claim 21, wherein an element to be scaled is selected from the group consisting of: a MOSFET ; a parallel combination of nMOS and pMOS transistors; an array of resistors; an array of capacitors; and an amplifier with gain control, with said amplifier providing input to said at least one integrator. 23. The method of claim 22, wherein the element to be time-scaled is an array of capacitors, wherein said array of capacitors is a digitally controlled, binary-weighted capacitor array. 24. The method of claim 16, wherein said time-scaling calibration is accomplished automatically via indirect tuning. 25. The method of claim 24, wherein said automatic indirect tuning employs an oscillator, a reference frequency, and an external clock to adjust a control voltage. 26. The method of claim 25, wherein said time-scaling calibration uses a crystal clock to set a precise time-scaling factor. 27. The method of claim 26, wherein the element to be scaled is selected from the group consisting of: a MOSFET ; a parallel combination of nMOS and pMOS transistors; an array of resistors; an array of capacitors; and an amplifier with gain control, with said amplifier providing input to said at least one integrator. 28. The method of any of claims 15 through 27, wherein said improved physical analog computer is adapted to process signals from a physical system selected from the group consisting of electrical-battery-management system, electrical-power-plant-control system, petroleum-refinery system, maritime -propulsion system, refrigeration-control system, heating-ventilation-and-air-conditioning (HVAC) system, and automobile- control system. 29. An improved integrator for use in a physical analog computer, said analog computer adapted to be incorporated in a physical system to be monitored, the physical system having needs, the physical analog computer having a computational speed, said improved integrator adapted to receive and process at least one input signal to be subjected to a forcing function, comprising: a means for receiving and processing an input time-scaling factor and introducing said input time-scaling factor to said forcing function and to the integrating operations of said improved integrator, wherein: said time-scaling factor is greater than 1 to slow down said analog-computational time, and said time-scaling factor is less than 1 to speed up said analog-computational time; said time-scaling being digitally controlled, whereby the introduction of said time-scaling factor adjusts the computational speed of said improved physical analog computer and response times to better match the needs of the associated physical system. 30. The improved integrator of claim 29, wherein said improved integrator is adapted to receive a sinusoidal input, the integrator having a unit-gain frequency having a gain magnitude, and said time-scaling is calibrated by ensuring that the gain magnitude of the unit-gain frequency of said improved integrator equals 1. 31. The improved integrator of claim 30, wherein said improved integrator’s type is selected from the group consisting of active resistor-capacitor integrator and transconductor-capacitance integrator. 32. The improved integrator of claim 30, wherein said scaling calibration is accomplished using at least one voltage-controlled resistor. 33. The improved integrator of claim 30, wherein said scaling calibration is accomplished automatically via direct tuning. 34. The improved integrator of claim 33, wherein said automatic direct tuning employs an external reference selected from the group consisting of frequency and resistance. 35. The improved integrator of claim 34, wherein said scaling calibration uses a crystal clock to set a precise time-scaling factor. 36. The improved integrator of claim 35, wherein an element to be scaled is selected from the group consisting of: a MOSFET ; a parallel combination of nMOS and pMOS transistors; an array of resistors; an array of capacitors; and an amplifier with gain control, with said amplifier providing input to said at least one integrator. 37. The improved integrator of claim 36, wherein the element to be scaled is an array of capacitors, wherein said array of capacitors is a digitally controlled, binary-weighted capacitor array. 38. The improved integrator of claim 30, wherein said time-scaling calibration is accomplished automatically via indirect tuning. 39. The improved integrator of claim 38, wherein said automatic indirect tuning employs an oscillator, a reference frequency, an external clock to adjust a control voltage. 40. The improved integrator of claim 39, wherein said time-scaling calibration uses a crystal clock to set a precise time-scaling factor. 41. The improved integrator of claim 40, wherein the element to be scaled is selected from the group consisting of: a MOSFET ; a parallel combination of nMOS and pMOS transistors; an array of resistors; an array of capacitors; and an amplifier with gain control, with said amplifier providing input to said at least one integrator. 42. The improved integrator of any of claims 29 through 41, wherein said improved integrator is incorporated into a physical analog computer that is adapted to process signals from a physical system selected from the group consisting of electrical-battery- management system, electrical-power-plant-control system, petroleum-refinery system, maritime -propulsion system, refrigeration-control system, heating-ventilation-and-air- conditioning (HVAC) system, and automobile-control system. 43. An improved electrical-power-generation plant having one or more electrical generators, each of which has at least one voltage regulator, at least one frequency regulator, and at least one load-sharing regulator, the electrical-power-generation plant having needs, comprising: at least one improved physical analog computer having at least one integrator adapted to receive and process at least one input signal to be subjected to a forcing function, said improved physical analog computer incorporated in any of said at least one voltage regulator, said at least one frequency regulator, or said at least one load-sharing regulator for any of said one or more electrical generators, said physical analog computer having a computational speed, said at least one physical analog computer comprising: a means for time-scaling said improved physical analog computer to better match analog-computational time with the needs of said improved electrical-power- generation plant by introducing an input time-scaling factor to said forcing function and to the integrating operations of said at least one integrator, wherein: said time-scaling factor is greater than 1 to slow down said analog- computational time, and said time-scaling factor is less than 1 to speed up said analog-computational time; said time-scaling being digitally controlled, whereby the introduction of said time-scaling factor adjusts the computational speed of said at least one improved physical analog computer and response times to better match the needs of said improved electrical-power-generation plant. 44. The improved electrical-power-generation plant of claim 43, wherein said at least one integrator has a sinusoidal input, said at least one integrator having a unit-gain frequency having a gain magnitude, wherein said time-scaling is calibrated by ensuring that the gain magnitude of the unit-gain frequency of said at least one integrator equals 1. 45. The improved electrical-power-generation plant of claim 44, wherein said at least one integrator’s type is selected from the group consisting of active resistor-capacitor integrator and transconductor-capacitance integrator. 46. The improved electrical-power-generation plant of claim 44, wherein said time-scaling calibration is accomplished using at least one voltage-controlled resistor. 47. The improved electrical-power-generation plant of claim 44, wherein said time-scaling calibration is accomplished automatically via direct tuning. 48. The improved electrical-power-generation plant of claim 47, wherein said automatic direct tuning employs an external reference selected from the group consisting of frequency and resistance. 49. The improved electrical-power-generation plant of claim 48, wherein said time-scaling calibration uses a crystal clock to set a precise time-scaling factor. 50. The improved electrical-power-generation plant of claim 49, wherein an element to be scaled is selected from the group consisting of: a MOSFET ; a parallel combination of nMOS and pMOS transistors; an array of resistors; an array of capacitors; and an amplifier with gain control, with said amplifier providing input to said at least one integrator. 51. The improved electrical-power-generation plant of claim 50, wherein the element to be scaled is an array of capacitors, wherein said array of capacitors is a digitally controlled, binary-weighted capacitor array. 52. The improved electrical-power-generation plant of claim 44, wherein said time-scaling calibration is accomplished automatically via indirect tuning. 53. The improved electrical-power-generation plant of claim 52, wherein said automatic indirect tuning employs an oscillator, a reference frequency, an external clock to adjust a control voltage. 54. The improved electrical-power-generation plant of claim 53, wherein said time-scaling calibration uses a crystal clock to set a precise time-scaling factor. 55. The improved electrical-power-generation plant of claim 54, wherein an element to be scaled is selected from the group consisting of: a MOSFET; a parallel combination of nMOS and pMOS transistors; an array of resistors; an array of capacitors; and an amplifier with gain control, with said amplifier providing input to said at least one integrator. 56. An improved electrical-battery-management system, the improved electrical-battery- management system having needs, the improved electrical-battery-management system comprising: at least one improved physical analog computer having at least one integrator adapted to receive and process at least one input signal to be subjected to a forcing function, the improved physical analog computer having a computational speed and said improved physical analog computer comprising: a means for time-scaling said improved physical analog computer to better match analog-computational time with the needs of said improved electrical-battery- management system by introducing an input time-scaling factor to said forcing function and to the integrating operations of said at least one integrator, wherein: said time-scaling factor is greater than 1 to slow down said analog- computational time, and said time-scaling factor is less than 1 to speed up said analog-computational time; said time-scaling being digitally controlled, whereby the introduction of said time-scaling factor adjusts the computational speed of said at least one improved physical analog computer and response times to better match the needs of said improved electrical-battery-management system. 57. The improved electrical-battery-management system of claim 56, wherein said at least one integrator has a sinusoidal input and said time-scaling is calibrated by ensuring that the gain magnitude of the unit-gain frequency of said at least one integrator equals 1. 58. The improved electrical-battery-management system of claim 57, wherein said at least one integrator’s type is selected from the group consisting of active resistor-capacitor integrator and transconductor-capacitance integrator. 59. The improved electrical-battery-management system of claim 57, wherein said time scaling calibration is accomplished using at least one voltage-controlled resistor. 60. The improved electrical-battery-management system of claim 57, wherein said time- scaling calibration is accomplished automatically via direct tuning. 61. The improved electrical-battery-management system of claim 60, wherein said automatic direct tuning employs an external reference selected from the group consisting of frequency and resistance. 62. The improved electrical-battery-management system of claim 61, wherein said time- scaling calibration uses a crystal clock to set a precise time-scaling factor. 63. The improved electrical-battery-management system of claim 62, wherein an element to be scaled is selected from the group consisting of: a MOSFET ; a parallel combination of nMOS and pMOS transistors; an array of resistors; an array of capacitors; and an amplifier with gain control, with said amplifier providing input to said at least one integrator. 64. The improved electrical-battery-management system of claim 63, wherein the element to be scaled is an array of capacitors, wherein said array of capacitors is a digitally controlled, binary-weighted capacitor array. 65. The improved electrical-battery-management system of claim 57, wherein said time- scaling calibration is accomplished automatically via indirect tuning. 66. The improved electrical-battery-management system of claim 65, wherein said automatic indirect tuning employs an oscillator, a reference frequency, an external clock to adjust a control voltage. 67. The improved electrical-battery-management system of claim 66, wherein said time- scaling calibration uses a crystal clock to set a precise time-scaling factor. 68. The improved electrical-battery-management system of claim 67, wherein an element to be scaled is selected from the group consisting of: a MOSFET; a parallel combination of nMOS and pMOS transistors; an array of resistors; an array of capacitors; and an amplifier with gain control, with said amplifier providing input to said at least one integrator. 69. An improved physical analog computer having at least one integrator adapted to receive and process at least one input signal to be subjected to a forcing function, said analog computer disposed to solve differential equations for simulation of physical, biological, or financial systems, the computer comprising: a means for time-scaling said improved physical analog computer to better match analog-computational time with the needs of said system being simulated by introducing an input time-scaling factor to said forcing function and to the integrating operations of said at least one integrator, wherein: said time-scaling factor is greater than 1 to slow down said analog-computational time, and said time-scaling factor is less than 1 to speed up said analog-computational time; said time-scaling being digitally controlled, whereby the introduction of said time-scaling factor adjusts the computational speed of said improved physical analog computer and response times to better match the needs of said system being simulated. 70. The improved physical analog computer of claim 69, wherein said at least one integrator has a sinusoidal input, the at least one integrator having a unit-gain frequency having a gain magnitude, wherein said time-scaling is calibrated by ensuring that the gain magnitude of the unit-gain frequency of said at least one integrator equals 1. 71. The improved physical analog computer of claim 70, wherein said at least one integrator’s type is selected from the group consisting of active resistor-capacitor integrator and transconductor-capacitance integrator. 72. The improved physical analog computer of claim 70, wherein said time-scaling calibration is accomplished using at least one voltage-controlled resistor. 73. The improved physical analog computer of claim 70, wherein said time-scaling calibration is accomplished automatically via direct tuning. 74. The improved physical analog computer of claim 73, wherein said automatic direct tuning employs an external reference selected from the group consisting of frequency and resistance. 75. The improved physical analog computer of claim 74, wherein said time-scaling calibration uses a crystal clock to set a precise time-scaling factor. 76. The improved physical analog computer of claim 75, wherein an element to be scaled is selected from the group consisting of: a MOSFET ; a parallel combination of nMOS and pMOS transistors; an array of resistors; an array of capacitors; and an amplifier with gain control, with said amplifier providing input to said at least one integrator. 77. The improved physical analog computer of claim 76, wherein the element to be time- scaled is an array of capacitors, wherein said array of capacitors is a digitally controlled, binary-weighted capacitor array. 78. The improved physical analog computer of claim 70, wherein said time-scaling calibration is accomplished automatically via indirect tuning. 79. The improved physical analog computer of claim 78, wherein said automatic indirect tuning employs an oscillator, a reference frequency, an external clock to adjust a control voltage. 80. The improved physical analog computer of claim 79, wherein said time-scaling calibration uses a crystal clock to set a precise time-scaling factor. 81. The improved physical analog computer of claim 80, wherein an element to be scaled is selected from the group consisting of: a MOSFET ; a parallel combination of nMOS and pMOS transistors; an array of resistors; an array of capacitors; and an amplifier with gain control, with said amplifier providing input to said at least one integrator. 82. A method of operating an improved physical analog computer having at least one integrator adapted to receive and process at least one input signal to be subjected to a forcing function, said analog computer disposed to solve differential equations for simulation of physical, biological, or financial systems, the system being simulated having needs, the analog computer having a computation speed, the method comprising the steps of: introducing an input time-scaling factor to said improved physical analog computer to better match analog-computational time with the needs of said system being simulated by introducing said input time-scaling factor to said forcing function and to the integrating operations of said at least one integrator, wherein: said time-scaling factor is greater than 1 to slow down said analog-computational time, and said time-scaling factor is less than 1 to speed up said analog-computational time; said time-scaling being digitally controlled, whereby the introduction of said time-scaling factor adjusts the computational speed of said improved physical analog computer and response times to better match the needs of said system being simulated. 83. The method of claim 82, wherein said at least one integrator has a sinusoidal input, the at least one integrator having a unit-gain frequency having a gain magnitude, wherein said time-scaling is calibrated by ensuring that the gain magnitude of the unit-gain frequency of said at least one integrator equals 1. 84. The method of claim 83, wherein said at least one integrator’s type is selected from the group consisting of active resistor-capacitor integrator and transconductor-capacitance integrator. 85. The method of claim 83, wherein said time-scaling calibration is accomplished using at least one voltage-controlled resistor. 86. The method of claim 83, wherein said time-scaling calibration is accomplished automatically via direct tuning. 87. The method of claim 86, wherein said automatic direct tuning employs an external reference selected from the group consisting of frequency and resistance. 88. The method of claim 87, wherein said time-scaling calibration uses a crystal clock to set a precise time-scaling factor. 89. The method of claim 88, wherein an element to be scaled is selected from the group consisting of: a MOSFET ; a parallel combination of nMOS and pMOS transistors; an array of resistors; an array of capacitors; and an amplifier with gain control, with said amplifier providing input to said at least one integrator. 90. The method of claim 89, wherein the element to be time-scaled is an array of capacitors, wherein said array of capacitors is a digitally controlled, binary-weighted capacitor array. 91. The method of claim 83, wherein said time-scaling calibration is accomplished automatically via indirect tuning. 92. The method of claim 91, wherein said automatic indirect tuning employs an oscillator, a reference frequency, and an external clock to adjust a control voltage. 93. The method of claim 92, wherein said time-scaling calibration uses a crystal clock to set a precise time-scaling factor. 94. The method of claim 93, wherein an element to be scaled is selected from the group consisting of: a MOSFET ; a parallel combination of nMOS and pMOS transistors; an array of resistors; an array of capacitors; and an amplifier with gain control, with said amplifier providing input to said at least one integrator. 95. An improved integrator for use in a physical analog computer, said analog computer disposed to solve differential equations for simulation of physical, biological, or financial systems, the system being simulated having needs, the physical analog computer having a computational speed, said improved integrator adapted to receive and process at least one input signal to be subjected to a forcing function, comprising: a means for receiving and processing an input time-scaling factor and introducing said input time-scaling factor to said forcing function and to the integrating operations of said improved integrator, wherein: said time-scaling factor is greater than 1 to slow down said analog-computational time, and said time-scaling factor is less than 1 to speed up said analog-computational time; said time-scaling being digitally controlled, whereby the introduction of said time-scaling factor adjusts the computational speed of said improved physical analog computer and response times to better match the needs of the associated system being simulated. 96. The improved integrator of claim 95, wherein said improved integrator is adapted to receive a sinusoidal input, the integrator having a unit-gain frequency having a gain magnitude, and said time-scaling is calibrated by ensuring that the gain magnitude of the unit-gain frequency of said improved integrator equals 1. 97. The improved integrator of claim 96, wherein said improved integrator’s type is selected from the group consisting of active resistor-capacitor integrator and transconductor-capacitance integrator. 98. The improved integrator of claim 96, wherein said scaling calibration is accomplished using at least one voltage-controlled resistor. 99. The improved integrator of claim 96, wherein said scaling calibration is accomplished automatically via direct tuning. 100. The improved integrator of claim 99, wherein said automatic direct tuning employs an external reference selected from the group consisting of frequency and resistance. 101. The improved integrator of claim 100, wherein said scaling calibration uses a crystal clock to set a precise time-scaling factor. 102. The improved integrator of claim 101, wherein an element to be scaled is selected from the group consisting of: a MOSFET ; a parallel combination of nMOS and pMOS transistors; an array of resistors; an array of capacitors; and an amplifier with gain control, with said amplifier providing input to said at least one integrator. 103. The improved integrator of claim 102, wherein the element to be scaled is an array of capacitors, wherein said array of capacitors is a digitally controlled, binary-weighted capacitor array. 104. The improved integrator of claim 96, wherein said time-scaling calibration is accomplished automatically via indirect tuning. 105. The improved integrator of claim 104, wherein said automatic indirect tuning employs an oscillator, a reference frequency, an external clock to adjust a control voltage. 106. The improved integrator of claim 105, wherein said time-scaling calibration uses a crystal clock to set a precise time-scaling factor. 107. The improved integrator of claim 106, wherein an element to be scaled is selected from the group consisting of: a MOSFET ; a parallel combination of nMOS and pMOS transistors; an array of resistors; an array of capacitors; and an amplifier with gain control, with said amplifier providing input to said at least one integrator. |
AND METHODS OF USE
CROSS-REFERENCE TO RELATED APPLICATION
This patent application hereby incorporates by reference U.S. Patent Application No. 62/683,742, filed June 12, 2018, for all purposes. Should any irreconcilable conflicts arise between this patent application and the teachings of U.S. Patent Application No. 62/683,742 for purposes of claim construction/interpretation, then this patent application’s teachings shall govern.
BACKGROUND
The solution of equations describing a physical problem evolves over a time scale determined by the form of the equations and the constants within them. An analog or hybrid computer normally solves time-scaled versions of those equations, and the solution to those versions evolves over a completely different time scale. However, sometimes it is desired to run an analog or hybrid computer slower than real time in order to ensure that the hardware can follow; e.g., if an ordinary differential equation (ODE) with expected time constants in the nanosecond (ns) range is being solved. Similarly, sometimes it is desired to operate an analog or hybrid computer faster than real time in order to save computation time; e.g., if an ODE representing automobile suspension is being solved.
What is needed is a robust and efficient means to accomplish time-scaling up or down, as required, in order to address the needs stated above.
BRIEF SUMMARY
The inventive disclosures described herein pertain to an improved physical analog computer that features one or more improved integrators that can be time-scaled with respect to an input signal in order to better match the time performance of the analog computing with needs of the real-world machine/system that the improved physical analog computer is incorporated into so that adverse effects of non-time-scaled operations are minimized or eliminated. The basic concept is to provide a means to introduce an input time-scaling factor to a forcing function and to the integrating operations of integrator(s) within the improved physical analog computer, wherein a time-scaling factor of greater than 1 is used to slow down said analog-computational time, and a time-scaling factor of less than 1 is used to speed up said analog-computational time.
The embodiments discussed herein include discussions of time-scaling calibrations, including automatic direct tuning and automatic indirect tuning of the subject systems.
The foregoing Brief Summary is intended to merely provide a short, general overview of the inventive disclosure described throughout this patent application, and therefore, is not intended to limit the scope of the inventive disclosure contained throughout the balance of this patent application, including any appended claims and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1A depicts one embodiment of an example graph of the original forcing function versus real time; that is, a non-time- scaled profile.
Figure IB depicts one embodiment of the example graph in Figure 1A post-time- scaling, with the resultant performance profile of a time-scaled forcing function versus machine time, wherein the resultant performance profile displays extended transitions over time; that is, a time-scaled profile.
Figure 1C depicts one embodiment of a non-time-scaled integrator profile, reflecting a steep output slope.
Figure ID depicts one embodiment of the integrator profile of Figure 1C, after subjecting the integrator to a time-scaling factor, which resulted in a marked reduction in the integrator output slope; i.e., a, extension of the time it takes to work through a given transient condition.
Figure IE depicts one embodiment of an example analog computer block diagram featuring two integrators, before any time-scaling is applied.
Figure IF shows the same system from Figure IE, but with time-scaling applied. (The initial conditions remain the same between Figures IE and IF.)
Figure 2A depicts one embodiment of a simple block diagram of input and output of an integrator.
Figure 2B depicts one embodiment of an integrator-tuning schema that employs a programmable amplifier with gain control can be used in front of the integrator to be time- scaled. The output of the amplifier effectively acts as an additional time-scale multiplier for the integrator to be time-scaled. Figure 2C depicts one embodiment of a block diagram of an integrator-tuning schema with an external reference and matched circuit (that is, indirect tuning), wherein the target integrator can be tuned before computation, and then the tuning circuitry is turned off.
Figure 2D depicts one embodiment of a basic integrator-tuning example.
Figure 2E depicts one embodiment of one alternative means to adjust time-scaling (if the use of MOSFET voltage-controlled resistors is not feasible); that is, a digitally controlled, binary-weighted capacitor array.
Figure 2F depicts one embodiment of a simplified block diagram of an integrator tuning system that uses an oscillator and a reference frequency.
Figure 2G depicts one embodiment of a simplified block diagram of an integrator tuning system that uses a frequency filter and a reference frequency.
Figure 2H depicts one embodiment of a simplified block diagram of an integrator tuning system that uses a MOSFET and a reference resistor to adjust a control voltage.
Figure 21 depicts one embodiment of another example of an oscillator-type of integrator-tuning system that employs an integrator-based oscillator, an external clock, comparator circuitry, and a loop filter to adjust the control voltage.
DETAILED DESCRIPTION
I. Overview
The inventive disclosures described herein pertain to an improved physical analog computer that features one or more improved integrators that can be time-scaled with respect to an input signal in order to better match the time performance of the analog computing with needs of the real-world machine/system that the improved physical analog computer is incorporated into so that adverse effects of non-time-scaled operations are minimized or eliminated. The basic concept is to provide a means to introduce an input time-scaling factor to a forcing function and to the integrating operations of integrator(s) within the improved physical analog computer, wherein a time-scaling factor of greater than 1 is used to slow down said analog-computational time, and a time-scaling factor of less than 1 is used to speed-up said analog-computational time.
The embodiments discussed herein include discussions of time-scaling calibrations, including automatic direct tuning and automatic indirect tuning of the subject systems. II. T erminologv
The terms and phrases as indicated in quotes (“”) in this Section are intended to have the meaning ascribed to them in this Terminology Section applied to them throughout this document, including the claims, unless clearly indicated otherwise in context. Further, as applicable, the stated definitions are to apply, regardless of the word or phrase’s case, to the singular and plural variations of the defined word or phrase.
The term“or”, as used in this specification, drawings, and any appended claims, is not meant to be exclusive; rather, the term is inclusive, meaning“either or both”.
References in the specification to“one embodiment”,“an embodiment”,“a preferred embodiment”,“an alternative embodiment”,“a variation”,“one variation”, and similar phrases mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least an embodiment of the invention. The appearances of the phrase“in one embodiment” and/or“in one variation” and similar phrases in various places in the specification are not necessarily all meant to refer to the same embodiment.
As applicable, the terms“about”,“approximately”, or“generally”, as used herein unless otherwise indicated, means a margin of ± 50%. It is to be appreciated that not all uses of the above terms are quantifiable such that the referenced ranges can be applied.
The term“analog computer,” as used in this specification, drawings, and any appended claims, refers to a type of computer that uses the continuously varying aspects of physical phenomena such as electrical, mechanical, or hydraulic quantities to model a problem being solved. In contrast, digital computers represent varying quantities in discrete quantities, as their numerical values change. Because an analog computer does not use discrete values, but rather continuous values, processes cannot be reliably repeated with exact equivalence. However, unlike digital-signal processing in digital computers, analog computers do not suffer from the discrete error caused by quantization noise. Analog computers are subject to signal errors/perturbations from induced electronic noise. Analog computers and/or hybrid analog-digital computers (“hybrid computers”) were often used in scientific and industrial applications to perform control and protective functions. For the purposes of the disclosures contained herein, all references to“analog computers” are intended to also encompass“hybrid computers.” III. An Improved Analog Computer Using Time-Scaling and Calibration
This Section III is directed generally to an improved analog computer that incorporates a means to effectively and efficiently time-scale up or down as needed for the solving of ordinary differential equations in real-world applications. Refer to Figures 1A through 2J.
A. General Description of Time-Scaline
Let: t : real time
T: machine time
And relate the two by a“time-scaling factor”, 71:
t = rit
Where: slow down
speed up
To time-scale the solution, two steps need to be performed:
1. Time-scale the forcing function (refer to Figures 1A and IB); and
2. Time-scale the integrating operations (as shown in the computer-block
diagrams in Figures 1C through IF).
Turning to Step 1, Time-scaling the forcing function involves the following:
Let: t : real time
T: machine time
And relate the two by a“time-scaling factor”, 71:
t = nt
Then, replace t with the machine time T divided by 71, such that:
Where: 71 ]> 1 : slow down
ΪT < 11 speed up
Figure 1A shows an example graph of the original forcing function x(t) versus real time t, and Figure IB shows an example graph of the resultant performance profile of a time- scaled forcing function X J versus machine time T, wherein the resultant performance profile displays extended transitions over time.
As an example, let an original forcing function be defined as: x(t ) = e -20f sin(40t)
To slow this forcing function down by a factor of 100, use 71 = 100;
This reduces to:
x(t ) = e _0 2T sin(0.4T)
The alert reader will appreciate that if the time-scaling factor tl had been less than 1, then the slope characteristics in Figure 1C would cause the integrator output curve to have an even steeper slope.
Turning to Step 2, and referring to the block diagrams of Figures 1C and ID, in the analog-computer, the only time-dependent elements are integrators. The non-time-scaled integrator profile shown in Figure 1C reflects a steep output slope, and the time-scaled (slow-down scaling) integrator profile shows a marked reduction in the integrator output slope; i.e., a, extension of the time it takes to work through a given transient condition. No other differences between the block diagrams of Figures 1C and ID are present.
Figure IE provides an example analog computer block diagram featuring two integrators, before any time-scaling is applied. Figure IF shows the same system from
Figure IE, but with time-scaling applied. The initial conditions remain the same between
Figures IE and IF :
In the new, time-scaled system of Figure 1A-6, all variables are time-scaled:
B. The Importance of Setting the Time-Scaling Factor Value
A time-scaling factor should ideally reflect a quantity that can be relied on; that is:
• The analog computer incorporated in a system/device must be robustly
calibrated against system/device tolerances, temperature, and power-supply voltage changes so that the time-scaling factor does not vary over time; and
• The value of the time-scaling factor must be accurately known.
In some systems; e.g., real-time control loops, the value of the analog-computing time-scaling factor is quite important. However, in some other systems, the value of the time-scaling factor does not really matter, though for certain applications; such as, e.g., in the simulation of physical systems; the value needs to be known. In other applications, the value of the time-scaling factor does not have to be accurately known; e.g., systems used to solve algebraic equations.
C. Time-Scaline Calibration
In many embodiments, an improved analog computer comprises integrators, adders, multipliers, fanout blocks, and nonlinear function generators. Of these, the only dynamical element (that is, time-dependent element) is the integrator. All other elements have time responses that are, ideally, infinitely fast, and thus are generally not configurable with respect to time. Consequently, it is necessary to create a means to accurately calibrate the time behavior of the integrators in the analog-computing system.
Refer to Figure 2A, which depicts a simple block diagram of input and output of an integrator. In Figure 2A, it is assumed that X and J have the same units/dimensions (e.g., both voltage or both current), although this is not necessary. When analyzing integrator performance, a commonly used parameter is the“unit-gain frequency”. This is defined for a sinusoidal input, and is the frequency at which the gain magnitude becomes the value of 1 : The time-scaling constant k depends on implementation details; for example:
• For an active resistor-capacitor integrator, kis of the form 1/RC
• For the transconductor-capacitor integrators on a chip, fis of the form G j n/ C where G m is a“transconductance” (which has dimensions of conductance; it is equal to 1/R, where R a resistance).
• In each of the above cases, /fis of the form 1/RC and has dimensions of inverse time.
Time-scaling factor /ffor a given integrator can be, for example, proportional to
1/R \ C \ . R is selected to provide the desired time-scaling factor k Resistors, and to a smaller extent, capacitors, have large fabrication tolerances and their respective values are dependent on temperature. Depending on the fabrication process, the RC product uncertainty can be as much as 30-40%. Thus, to set the product accurately, two actions need to be performed:
• Provide a means to vary RC, and
· Provide a means to reliably set the value of RC.
One way to address these two tasks, a voltage-controlled resistor can be implemented using a MOSFET, or in a preferred variation, using a parallel combination of nMOS and pMOS transistors, provided that the supply voltage is large-enough to accomplish this.
Varying the gate voltage of the MOSFET, or of the parallel-combination of the nMOS and pMOS transistors, as applicable, varies their effective resistance value, and thus varies the value of time-scaling factor k This, therefore, makes the RC product adjustable. Flowever, a means to set the value precisely that is independent of tolerances and temperature is still needed. To automatically set the RC product value, techniques that have been used to make the frequency response of the integrated analog filters are borrowed, and many such techniques known in the art have been developed for this purpose. As examples, the following are two such techniques, appropriate for an analog computer:
Direct Tuning: The integrators to be used are tuned directly. This is the most accurate approach, but also represents significant overhead; or • Indirect Tuning: A representative integrator is tuned, and the required tuning voltage or current is applied to all other integrators. These are thus automatically adjusted, due to the high degree of matching achievable on integrated circuits (for example, within better than l%-2% for the entire set of integrators on a chip). Automatic Tuning ( Direct Version)
Referring to Figure 2C, the integrator can be tuned before computation, and then the tuning circuitry is turned off. Alternatively, tuning can be performed while computation is ongoing; however, unless the computational operations are long, concurrent tuning and computational operations is not needed/desired and should be avoided in order to reduce the chances of the tuning circuitry causing interference with the computational circuitry.
For automatic tuning, the following items should be considered:
• The external reference to be used: E.g., frequency or resistance
• The Mode of Tuning: Direct (tune the filter/integrator itself) or Indirect (tune a matched replica structure, then apply the tuning to the matched operational structure)
o If a Replica Structure to Be Used (Indirect Tuning): An integrator and an integrator-based oscillator or filter is preferably needed.
• Elements to Be Adjusted (i.e., Time-Scaled): capacitors, resistors, and/or gain elements
• When to Tune: continuously or occasionally
• Type of Tuning: digital or analog
• Tuning Approach: open-loop or closed-loop
Referring to a basic integrator-tuning example shown in Figure 2D, the automatic tuning system adjusts time-scaling factor /fund I ti attains a precise value T set by a crystal clock. Then time-scaling factor Jcis precisely set:
If the use of MOSFET resistors is not feasible, then an array of resistors or capacitors can be used instead. For example, a digitally controlled, binary- weighted capacitor array can be used, as depicted in Figure 2E. Automatic Tuning ( Indirect Version )
Figure 2F depicts a simplified block diagram of an integrator-tuning system that uses an oscillator and a reference frequency. Figure 2G depicts a simplified block diagram of an integrator-tuning system that uses a frequency filter and a reference frequency. Figure 2H depicts a simplified block diagram of an integrator-tuning system that uses a MOSFET and a reference resistor to adjust a control voltage V c.
Figure 21 depicts an example of an oscillator-type of integrator-tuning system that employs an integrator-based oscillator, an external clock, comparator circuitry, and a loop filter to adjust the control voltage V c.
Alternatively, in another example shown in Figure 2B, if variable/settable resistors and capacitors are not available, then a programmable amplifier a with gain control can be used in front of the integrator to be time-scaled. The output of the amplifier effectively acts as an additional time-scale multiplier for the integrator to be time-scaled.
The alert reader will also recognize that more-elaborate schemes for
introducing/adjusting a time-scaling factor kmay be used to take into account other second- order effects such as parasitic capacitances and associated phase shifts.
In some embodiments for which the accuracy of the analog-computer time-scaling factor is not important, so long as it is known, the following needs to be performed in addition to the tuning schemes already discussed above:
• During calibration, measure the integrator gain constant k, and
• Use the measured integrator gain constant kon a digital computer to interpret the results accordingly.
For example, referring again to the integrator tuning in Figure 2D:
This technique can be implemented in hardware or in software, and assumes that once integrator gain constant fis determined, it does not vary during computation. Flowever, if it does vary, then either recalibration is required often or direct tuning (as already described above) needs to be performed so that integrator gain constant Jcis constantly kept“in tune”, or the value of k needs to be re-measured.
In summary, the time-scaling factors for analog computers must be carefully addressed. In real-time control, the time-scaling factor must be known and accurately set. A variety of tuning schemes, inspired by integrated analog filter tuning, can be used as described earlier in this Section III. In some applications, the time-scaling factor may not have to be set, but it must be accurately known; this can be accomplished by measuring the time-scaling factor and comparing it to an external time reference. For applications that only involve solving algebraic equations, the value of the time-scaling factor may not be important.
IV. Alternative Embodiments and Other Variations
The various embodiments and variations thereof described herein, including the descriptions in any appended Claims and/or illustrated in the accompanying Figures, are merely exemplary and are not meant to limit the scope of the inventive disclosure. It should be appreciated that numerous variations of the invention have been contemplated as would be obvious to one of ordinary skill in the art with the benefit of this disclosure.
Flence, those ordinarily skilled in the art will have no difficulty devising myriad obvious variations and improvements to the invention, all of which are intended to be encompassed within the scope of the Description, Figures, and Claims herein.
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