IMPROVED DIGITAL SYNTHESIZER

BACKGROUND OF THE INVENTION

Field of the Invention The present invention relates generally to frequency modulated signal synthesizer circuits as utilized in music synthesizers, and more particularly to an FM synthesizer circuit having self-modulation and output waveform shape selection features.

Description of the Prior Art Many patented and unpatented circuits have been developed for synthesizing music sounds electronically. Early digital FM synthesizer circuits are taught in U.S. Patent 4,018,121 issued 4/19/77 to Chowning, and in the technical article entitled "Design of a Digital Oscillator which will Generate up to 256 Low Distortion Sine Waves in Real Time", authored by John Snell, published in April, 1977 by Computer Music Journal, pages 4-25. Further relevant prior art includes U.S. Patent No. 4,249,477, issued February 10, 1981, to Tomisawa and U.S. Patent 4,813,326, issued March 21, 1989 to Hirano et al . These patents and the technical article by Snell evidence the ever increasing circuit complexity that has been utilized in the ongoing effort to better duplicate the complex tonal qualities of various music instruments

electronically. More recently, digital FM synthesizer devices have been marketed by Yamaha Corporation that demonstrate further evolutionary steps in electronic circuit complexity and output signal tonal richness, all to better emulate real music instrument sound qualities. The present invention constitutes a further advance in digital FM synthesizer circuitry.

SUMMARY OF THE INVENTION The present invention is an improved apparatus for digitally synthesizing a musical sound. It utilizes a phase angle generator component, a quarterwave sine logic component, a wave constructor component, and a modulation logic component . The phase angle generator component is operatively connected to the quarterwave sine logic component, such that a phase angle signal value from the phase angle generator component is fed to the quarterwave sine logic component. The quarterwave sine logic component receives the phase angle signal value and outputs a first quadrant sine signal value. The wave constructor component is operatively connected to the quarterwave sine logic component to receive a successive plurality of first quadrant sine signal values. It constructs a pre-selected output waveform signal value from the plurality of first quadrant sine signal values. The modulation logic component is operatively connected to the wave generator component and to the angle generator component. The modulation logic component receives successive ones of the

output waveform signal values and creates a self- modulation signal value. It then outputs the self- modulation signal value to the angle generator component for usage in creating a further phase angle signal value. The circuit components are multiplexed to provide repeated signal generation steps to ultimately create an output signal. It is an advantage of the present invention that it provides an improved digital FM synthesizer circuit having rich and complex output signals to better emulate true musical instruments. It is another advantage of the present invention that it provides a digital FM synthesizer circuit having improved self-modulation signal features. It is a further advantage of the present invention that it provides an improved digital FM synthesizer circuit having improved output waveform shape construction logic and circuitry for the creation of more complex and real-sounding output signals. These and other features and advantages of the present invention will be understood by those skilled in the art upon examination of the following detailed description of the invention. However, the invention is not to be limited by the detailed description, but rather is intended to include all modifications hereto as would be obvious to one skilled in the art upon understanding the detailed description of the present invention.

IN THE DRAWINGS Fig. 1 is a schematic diagram of the FM synthesizer of the present invention; Fig. 2 is a detailed schematic diagram of the components comprising the FM signal generator circuit of the present invention; Fig. 3 depicts the various output waveform shapes that are selectable by the program control logic of the present invention; Fig. 4 depicts the angle wave select logic of Fig. 2 of the present invention; Fig. 5 depicts the multiplexer 78 of Fig. 2 of the present invention; Fig. 6 depicts the combinatorial logic portion of the wave constructor of Fig. 2 of the present invention; Fig. 7 depicts the wave multiplexer logic of the wave constructor of Fig. 2 of the present invention; Fig. 8 is a schematic diagram depicting a time multiplexed series circuit utilizing the FM signal generator circuit of the present invention; and Fig. 9 is a schematic diagram depicting a time multiplexed parallel circuit utilizing the FM signal generator circuit of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS This patent application claims the priority of U.S. Patent application 08/340,050 filed November 14, 1994, the disclosure of which is hereby incorporated herein as though set forth in full. FIG. 1 is a block diagram of the basic organization of a digital synthesizer 10 including a host interface 12, a register table 14, a Frequency Modulation (FM) synthesizer engine 16, and an output accumulator 18. The FM synthesizer engine 16 is a multiplexed device that is configured in the preferred embodiment to act as 36 (n=36) virtual FM signal generators. The virtual signal generators (n=l-36) are typically configured in pairs to create a frequency modulated signal, however other multiplexed combinations of the virtual signal generators are contemplated and discussed herebelow. The output accumulator 18 accumulates the successive signals from the virtual FM signal generators that comprise the FM synthesizer engine 16 and sends an output signal to a digital to analog converter 22. The digital to analog converter 22 converts the signal from the accumulator 18 to its analog form and directs it to a speaker system 24 (which may include a stereo amplifier system) for final output. Thus, stereo or greater numbers of output signals, implemented with multiple output accumulators, digital to analog converters and speakers are also contemplated. In the preferred embodiment the host interface 12 is a bi-directional data bus that provides a means of

transferring address and data information between a host computer system 20 and the synthesizer 10. The data and address information received from the host system 20 via the host interface 12 is stored in the register table 14. The host interface 12 also includes a set of control signals that regulates both access and data transfer activities between the host system 20 and the synthesizer's register table 14. In the preferred embodiment, the register table 14 is configured with a set of 243 registers, organized in two groups, whose contents will determine how each of the virtual FM signal generators (n=l-36) of the FM synthesizer engine 16 will operate. Based on the values from the register table 14, the FM synthesizer engine 16 generates complex signals having the amplitudes, frequencies, and other parameters required to produce a desired audio output signal. The functional components of the virtual FM signal generator (n=l-36) include an angle generator 28, a sine logic device 30, an envelope generator 32, a wave constructor 34, and modulation logic 38. The angle generator 28 receives the initial parameter values that specify the initial frequency and sound characteristics of a desired sound signal from the register table 14. In specific situations and at specific times (discussed hereinafter) the angle generator also receives an input signal from the modulation logic 38. The angle generator 28 then determines a phase angle value p(t) and supplies it as the input signal to the sine device 30. The sine logic device 30 is implemented in

combinatorial logic and it translates the input phase angle p(t) to its logarithmic sinusoidal equivalent as a function of time to provide an output value y(t)= log(sin(p(t) ) ) which is output to the wave constructor 34. In the preferred embodiment, the sine logic device 30 is a quarterwave sine logic device that calculates output values as though the phase angle input p(t) were in the first quadrant (0-90°) . For values of p(t) that are greater than 90° the sine logic device 30 is provided with a signal Q from the angle generator 28 indicating the quadrant of the value of the input angle p(t) . The quadrant indicating signal Q is also output to the wave constructor 34 for use therein in the construction of the output signal o(t) . The envelope generator 32 receives appropriate parameter values from the register table 14 fcr attack, decay or release rates, and calculatT ' ..• a*:rropriate amplitude or envelope parameter e *- <-.* . -larithmic value for the desired waveform. Lτ.-r»- -:--_ -..αted, the envelope parameter e(t) is forwarded tc the wave constructor 34. The wave constructor 34 performs a number of functions, the first of which is to combine the logarithmic envelope parameter with the logarithmic sinusoidal output value y(t) received from the sine logic device 30. The wave constructor 34, under program control, then creates the output signal o(t) for the virtual FM signal generator (n=l) . A detailed description of the functions of the angle generator 28, sine logic 30 and wave constructor 34 is provided herebelow with the aid

of Fig . 2 . The output o(t) from the first virtual signal generator (n=l) is passed under program control to either the accumulator 18 or to the modulation logic 38, as is discussed in detail herebelow. The modulation logic 38, under program control from signals from the register table 14, can direct the output signal o(t) back into the angle generator 28 of the first virtual signal generator (n=l) for a self modulation effect, or direct the output signal o(t) to the angle generator 28 of the second virtual signal generator (n=2) , as is described in greater detail herebelow. In this manner the signal from the first virtual signal generator (n=l) is used to modulate the signal generated by the second virtual signal generator (n=2) . By allowing the signal from the first virtual signal generator (n=l) to modulate the ε i ir.a . αer.erated by the second virtual generator (n=2 , ^• -..•• .* _' •. _' ..-ar-.t audio signal o(t) ₂ produced by the F»- -. ^• ..:* ... signal generator contains the carrier freq-- *.. -y .»•: • : r-ed by the second generator (n=2) modulated ana a--grr.er.ted by the output signal o(t), of the first virtual signal generator (n=l) . Thus the components and complexity of o(t) ₂ can be changed by merely altering either the frequency or amplitude components of o(t)j. The output signal o(t) ₂ from the second virtual signal generator (n=2) (where the control program dictates) is then sent to the accumulator 18 to be combined with the signals from the other virtual signal generators (n=3-36) for final conversion by the digital to analog converter 22 and transmission through

the speaker system 24. Reference is now made to Fig. 2 that shows the internal structure of the angle generator 28, sine logic 30, wave constructor 34 and the modulation logic 38 of the virtual signal generators (n=l-36) . As illustrated, the angle generator 28 includes a basic phase logic 50, an adder 52, an accumulator register 54, rhythm phase logic 56 and a second adder 58. The angle generator 28 receives the basic parameters from the register table 14, to calculate a base phase angle increment Δp(t) , and it forwards this parameter Δp(t) to adder 52. The adder 52 combines the base phase angle increment Δp(t) with a self-modulation signal value 60 that is generated at specific time increments by the modulation logic 38 from a fed back output signal of the virtual signal generator (n=l) , as is discussed more fully herebelow. The output of the adder 52 is then fed to an accumulator register 54 which operates in a FIFO manner. The signal from the accumulator register 54 is then fed to the rhythm phase logic 56 which modifies the input phase angle data to output a phase angle signal with a rhythmic component. The output phase angle signal from the rhythm phase logic 56 is fed to the adder 58 wherein it is combined at specific time increments with a signal 62 from the modulation logic 38 representative of output data from a prior output signal (in a time multiplexed manner) of the virtual signal generator. The output of the adder 58 then becomes the actual phase angle input signal p(t) to the sine logic device 30. The adder 58

also determines the quadrant (Q or QUAD [1:0]) of the phase angle p(t) and supplies that value Q to the sine logic 30 and the wave constructor 34. The quadrant identifying signal Q is determined utilizing the two most significant bits of the added signal within the adder 58. The value of the phase angle p(t) is determined as the eight least significant bits of the signal from the adder 58. The digital synthesizer 10 includes an output waveform shape selection signal WS, whereby the desired waveform shape of the output signal o(t) may be selected. As depicted in Fig. 3, various values of WS are associated with various output signal waveform shapes; such that WS=0 creates a sine wave, WS=1 creates a half sine wave, WS=2 creates a rectified sine wave, WS=3 creates rectified quarterwaves, WS=4 creates a doubled frequency sine wave, WS=5 creates a rectified doubled frequency sine wave, WS=6 creates a square wave, and WS=7 is a periodic wave which utilizes a halving of the phase angle value, wherein the first two quadrants of the waveform represented by WS=7 is represented by the value anti-log (p(t)) , and the second two quadrants are represented by the value anti-log (1- p(t)) , as will become clear from the following description. The numerical value of the waveform shape selection signal WS (0-7) is stored in a register 14 for input to the virtual signal generators (n=l-36) at appropriate times. The numerical value of WS is program selected to cause the virtual signal generators (n=l-36) to create the specific output waveform shapes to better enable the

synthesizer 10 to emulate specific musical instrument sounds. Thus, different waveform shapes (different values of WS) are utilized for example when the digital synthesizer 10 emulates a drum sound and when it emulates a violin.

Returning to Fig. 2, the angle wave select logic 70 utilizes the input signals WS, Q and p(t) to determine a final phase angle value (fp(t) or FINALPHASE [7 :0] ) that is output to the combinatorial logic one-quarter sine wave element 74 and to a multiplexer 78. The logic construct that is utilized within the angle wave select logic 70 is set forth in the following table which is keyed to the angle wave select logic 70 depicted in Fig. 4.

LOGIC TABLE I

S Q = QUAD [1:0] fp(t) = FINALPHASE [7:0]

0,1,2,3; if QUAD [1:0] = 1, FINALPHASE [7:0] = P' [7:0] else FINALPHASE [7:0] = P[7:0]

4,5; if P7 = 1, FINALPHASE [7:0] = P' [7:0] ,P7 else FINALPHASE [7:0] = P[7:0] , P7

6; FINALPHASE [7:0] = 11111111

7; FINALPHASE [7:0] = P[7:0]

The output signal (s(t) or SINDATA[11 : 0] ) of the combinatorial logic 74 is the logarithm of the sine of final phase angle value fp(t); that is, s (t) =log(sin(fp (t) ) ) , and this value is fed to the multiplexer 78.

The input signals to the multiplexer 78 are Q and fp(t) on one input line, s(t) on a second input line and WS on a third input line. The signal (y(t) or P[11:0]) that is output from the multiplexer 78 is controlled by

the value of WS according to the logic construct set forth in the following table which is keyed to the multiplexer 78 depicted in Fig. 5.

LOGIC TABLE II

Input signal = QUAD [1:0] , FINALPHASE [7 : 0] Input signal = s(t) = SINDATA[11 : 0] Input signal = WS[2:0] Output signal = y(t) = P[11:0] where PD[9:0] = QUAD [1:0], FINALPHASE [7 : 0] if PD[9] = 1; S[8:0] = PD' [8:0] else S[8:0] = PD[8:0] now using S [8 : 0] if WS = 7; P[11:0] = S[8:0] , '000' else P[11:0] = SINDATA[11:0]

P[11:0] is then latched in register 80.

The output signal P[11:0] from the sine logic 30 is then fed to an input register 80 of the wave constructor 34. As is further depicted in Fig. 6, a second register 82 within the wave constructor 34 holds an envelope determining signal value (e(t) or Amplitude A[8:0] ) from the envelope generator 32. At appropriate time increments the signal values from registers 80 and 82 are combined in an adder 84. Because the signals from registers and 80 and 82 are logarithmic values, the addition of the signals in adder 84 is equivalent to a multiplication of the two signal values. The signal output (CO,AD[8:0]) from adder 84 is fed to a combinatorial logic device 88. Additionally, the two least significant bits (A[2:0]) of the output signal from register 80 is also input directly to the combinatorial logic device 88. The Logic Table III below sets forth the signal processing logic of the

combinatorial logic device 88 as shown in Fig. 6

LOGIC TABLE III

Adder 84 sums the 9 MSB's of the Sine value, P[ll:3], with the Amplitude A[8:0] to generate a nine bit output, AD[8:0] , and carry-out bit, CO.

Combinatorial Logic 88 performs the following:

If CO = 1, WCNT[3:0] = '0000' MULADD[7:0] = '11111111'

If CO = 0, WCNT[3:0] = AD' [8:5] MULADD[7:0] = AD[4:0] , P[2:0]

Effectively, the adder and combinatorial logic perform the following if adder does not overflow (CO = 0) ,

MULADD[7:0] = P[7:0] + A[4:0] , P[2:0] The 8 LSB's of Ptll:0] are added with the 5 LSB's of A [8:0] concatenated with P[2:0]

WCNT[3:0] = (P[ll:8] + A[8:5])' if adder overflows (CO = 1)

MULADD[7:0] = '11111111' WCNT[3:0] = '0000'

A first signal value MULADD[7:0] output from the combinatorial logic device is input to the anti-log logic 92. This signal MULADD[7:0] generally comprises the added logarithmic values of the logarithmic signals from registers 80 and 82, as added in the adder 84. The anti- log logic 92 then converts the logarithmic signal value to a linear signal value (WFM[9:0]) and this linear signal output from the anti-log logic 92 is fed to a register 94.

A second output signal WCNT[3:0] from the combinatorial logic 88 is output to register 96. This signal is a logarithmic value that defines the area of logarithmic space in which the waveform represented by signal MULADD[7:0] resides. The creation of the two

signals WCNT[3:0] and MULADD[7:0] permits the utilization of a smaller anti-log logic device than would otherwise be necessary. The wave constructor 34 also includes a wave construction logic device 100, the inputs to which are the quadrant and wave selection signals Q and WS respectively. The wave construction logic device 100 utilizes the selected wave shape value WS (as depicted in Fig. 3) and the quadrant Q of the signal being processed, to output an invert signal I to register 104 and a kill signal K to register 108. The signals in registers 104 and 108 are passed to registers 112 and 116 respectively, such that the invert and kill signals 112 and 116 respectively correspond in a signal timing sense with the signals resident within registers 94 and 96. The wave multiplexer logic 120 within the wave constructor 34 functions to create the output waveform value (o(t) or SLOTOUT[12 :0] ) , and it is further depicted in Fig. 7. It is to be generally understood that the output signal A[9:0] from register 94 to multiplexer 120 represents a one quarter sine wave function, in that it generally represents the sine logic signal output signal y(t) from the one-quarterwave sine logic 30 multiplied by the envelope generator signal e(t) from envelope generator 72. Thus, to create the various wave shapes depicted in Fig. 3, and represented by various values of WS, the wave function signal values from registers 94 and 96 must be acted upon by the kill and invert signals from registers 116 and 112, in order to construct and output the various

wave shapes depicted in Fig. 3. The operation of the wave multiplexer logic 120 is set forth in Logic Table IV as keyed to Fig. 7.

LOGIC TABLE IV

1. A[9:0] is a linear value, while WS[3:0] is the logarithmic value that defines the area of logarithmic space in which the waveform resides.

2. A[9:0] is mapped to the according area of linear space as SLOTOUT[12 :0] as shown below: (LSR = Logic Shift Right, LSL = Logical Shift Left) .

3. The KILL signal is used as an enable signal to the mapping shown below. If KILL = 1, SLOTOUT [12:0] = 0.

4. The INVERT signal inverts the result of the mapping below.

S[3:0] (hexadecimal values) SLOTOUT[12:0] = o(t)

0 0

1 0

2 0

3 0

4 A[9:0] LSR 8 bits

5 A[9:0] LSR 7 bits

6 A[9:0] LSR 6 bits

7 A[9:0] LSR 5 bits

8 A[9:0] LSR 4 bits

9 A[9:0] LSR 3 bits

A A[9:0] LSR 2 bits

B A[9:0] LSR 1 bit

C A[9:0]

D A[9:0] LSL 1 bit

E A[9:0] LSL 2 bits

F A[9:0] LSL 3 bits

For instance, where WS=0, a full sine wave is selected as the desired output waveform shape (see Fig. 3) . To construct this waveform shape, the first quadrant

one-quarter wave output signals from register 94 and 96 are output in an unchanged manner from the multiplexer logic 120. The second set of one-quarterwave output signals from registers 94 and 96 represent the second quadrant of the WS=0 full sine wave. The output values from registers 94 and 96 represent the second quadrant values in that the final phase angle signal fp(t) was phase inverted in the angle wave select logic 70. These values are also output in an unchanged manner from the multiplexer logic 120. Thereafter, registers 94 and 96 output a third set of one-quarter wave signals to represent the third quadrant of the full sine wave, and the wave multiplexer logic utilizes the invert signal from register 112 to place a negative value on the output values from the multiplexer logic 120. To create the fourth quadrant full sine wave (WS=0) values, a fourth set of one-quarterwave signals from registers 94 and 96 representing phase inverted sine logic outputs (as output in the second quadrant) is inverted with a negative value using the invert signal, such that the wave multiplexer logic output signal o(t) corresponds to the fourth quadrant of a full sine wave. In this manner, four successive sets of one-quarterwave signal values from registers 94 and 96 are processed by the wave multiplexer logic 120 to construct the desired WS=0 full sine wave output signal o(t) . To create the half sine wave output signal corresponding to WS=1, the first half of the sine wave is constructed from the first two sets of one-quarterwave

outputs of registers 94 and 96 in the manner of a full sine wave described immediately above. Thereafter, the wave multiplexer logic 120 receives the kill signal from register 116, whereupon the next two sets of one- quarterwave input signals from register 94 and 96 are ignored, and a zero output signal is produced by the wave multiplexer logic 120. In this manner, the desired WS=1 half sine wave output waveform is created. The rectified full sine wave represented by WS=2 is created from four sets of one-quarter sine wave outputs of registers 94 and 96 by simply repeating for quadrants three and four the multiplexer steps utilized to create the first two quadrants of the full sine wave, as described hereabove; that is, without utilizing the invert signal. In this manner, a rectified full sine wave is constructed from four sets of one-quart rwav- signals output from registers 94 and 96. The quarterwave rectified ε_r.»- w.v :• ^■ ; : ♦ ^■ 5-τ.ted by WS=3 is created by outputting .i : :rr* .«•• *. of one- quarterwave signals and a waveform inverted third set of one-quarterwave signals from registers 94 and 96 through wave multiplexer logic 120, and utilizing the kill signal from register 116 to cause the wave multiplexer logic to output zero for the second and fourth sets of one- quarterwave output values from the registers 94 and 96. In this manner the desired output waveform shape represented by WS=3 is constructed by the wave multiplexer logic 120. The output waveform shapes represented by WS=4 and

WS=5 are doubled frequency waveform shapes corresponding to WS=0 and WS=2 respectively. These doubled frequency waveform shapes are created initially by the angle wave select logic 70 when WS=4 or 5 is input thereto. The doubled frequency one-quarterwave signal values therefore become resident in registers 94 and 96 in a time synchronized manner with the quadrant and wave select determined values for the kill and invert signals from the wave construction logic 100. Thus, the wave multiplexer 120 constructs the output waveform shapes represented by WS=4 and WS=5 in the same manner as output waveform shapes represented by WS=0 and WS=2 respectively as is described hereabove. The square wave output waveform shape represented by WS=6 is generated by the wave multiplexer logic 120 utilizing signal values from registers ^Q -. and 96, along with the invert signal from register 111 Tr.e output signals from registers 94 and 96 fc: t.-.- l.rr* quadrant one-quarter wave are all equal tc one : . and these values are output directly by the wave multiplexer logic 120. In fact, these output values are equal to 1.0 times e(t) , and thus are only equal to one (1) if e(t) equals one (1); however for ease of description purposes e(t) shall be assumed to be equal to one (1) in this discussion. Likewise, the output values from registers 94 and 96 corresponding to the second quadrant one-quarter wave are also equal to one (1) and these values are likewise output directly by the wave multiplexer logic 120. The output values from registers 94 and 96 for the

third quadrant one-quarter wave are also equal to one (1) , however the invert signal from register 112 is utilized by the wave multiplexer logic 120 to output a minus one (-1) value in the third quadrant. Likewise, the output values from registers 94 and 96 for the fourth quadrant one- quarter wave signals are also equal to one (1) , and these values are then inverted by the wave multiplexer logic based upon an invert signal from register 112, such that the output becomes minus one (-1) . In this manner, the square wave waveform shape (WS=6) is constructed from four quadrants of one-quarter wave waveshapes from registers 94 and 96, each of whose value is equal to one (1) . The output waveform shape represented by WS=7 is created from output signals from registers 94 and 96. The multiplexer logic 120 creates this waveform in essentially the same manner as the creation of the full sine wave waveform represented by WS=0. That is, output signals from registers 94 and 96 representing quadrants one and two are successively output in their unchanged value, and output signals representing quadrants three and four are inverted by the wave multiplexer logic based upon an invert signal from register 112. The output signal o(t) from the wave multiplexer logic 120 is fed to the modulation logic 38 as previously indicated. Within the modulation logic 38, the signal o(t) is fed to an AND gate 130 and to a first sample register 134 of a self-modulation circuit 136. The self- modulation circuit 136 also includes a second sample register 140, a third sample register 144, a subtractor

148 and a multiplier 152. The output signal 60 from the self-modulation circuit 136 passes from the multiplier 152 to the adder 52 of the angle generator 28. For each sample period of the synthesizer 10 an output value o(t) is placed in sample register 134. Each time the sample period, the signal stored in sample register 134 is transferred to sample register 140 and a new output signal from wave multiplexer logic 120 is stored in sample register 134. As the sample period repeats again, the signal in sample register 140 is transferred to sample register 144 and the signal from register 134 is transferred to register 140. Thus, after the first three sample periods, registers 134, 140 and 144 each contain successive output signals from the wave multiplexer logic 120. Thereafter, in the next sample period the signal from register 144 is passed to the subtractor 148, and at the same time, a signal from register 134 is also passed to the subtractor 148. The difference between the two signals in subtractor 148 is then output to the multiplier 152 for multiplication by a constant K, and the output signal from the multiplier (K times the difference signal) is the signal 60 that is fed to the adder 52 of the angle generator 28. Thus, it is to be understood that the self-modulation circuit 136 provides an output signal 60 that represents the difference of two non-successive output signals from the wave multiplexer logic 120. The significance of the self- modulation circuit 136 is to eliminate certain signal irregularities of the digital synthesizer when the value

of the output signal o(t) approaches zero, as when the value of a sine wave function approaches zero at angles zero, 180° and 360°. As previously indicated, the output signals o(t) from the wave multiplexer logic 120 are fed to an AND gate 130 within the modulation logic 138. Upon the receipt of a control signal M, the AND gate 130 is activated and the signal o(t) then output from multiplexer 120 is fed to a register 160, whereafter it is next fed as the modulation signal 62 from a first virtual signal generator (n=l) to the modulation input adder 58 of the angle generator 28 of a second virtual signal generator (n=2) . The usage of the FM synthesizer engine 16 in successive signal processing steps, that is, as the virtual signal generators (n=l,2,3...) is best understood with the aid of Figs. 8 and 9. Fig. 8 depicts the virtual signal generator engine 16 in a time multiplexed configuration for n=l and n=2 in a series circuit configuration. As depicted therein, in a first series of sample periods a first output signal o(t) ' is constructed utilizing the angle generator 28, sine logic 30, envelope generator 32 and wave construction 34 elements of the generator 40 as discussed above. The first output signal o(t)' is fed to the modulation circuit 38 whereupon it is fed back during the next sample period as the self-modulation signal 60. The generator then incorporates the self-modulation signal 60 within the angle generator 28 to create a second output signal o(t), utilizing the angle generator 28, sine logic 30, envelope

generator 32 and wave construction 34 components in the manner previously discussed. The second output signal o(t) _! is fed to the modulation circuit 38, whereupon it is outputted as signal 62 during the next sample period to the angle generator 28 of the second signal generator circuit (n=2) , as discussed hereabove. The signal generator circuit 40 now functions as the second virtual signal generator (n=2) and an output signal o(t) ₂ is constructed utilizing the angle generator 28, sine logic 30, envelope generator 32 and wave construction 34 components of the generator 16 as discussed above. It is therefore to be understood that the circuit 40 comprising the signal generator components has been essentially utilized four times in a time multiplexed manner to create the ultimate output signal o(t) ₂ . The first three circuit usages were performed to create the self-modulation signal 60; the fourth circuit usage was to create the modulation signal 62; the fifth circuit usage was to create the ultimate output signal o(t) ₂ . It is noted that the modulation circuit 38 is not utilized in the fifth passage through the circuit components because to do so would create a signal such as 60 or 62 whereby a sixth passage through the circuit elements would be necessary to create an output signal from the wave constructor 34. Thus, the virtual generator configuration depicted in Fig. 4 is a series circuit configuration wherein the first generator (n=l) includes a self-modulation time incremented step, and the second generator n=2 does not include a self- modulation time incremented step.

Fig. 9 depicts a parallel circuit implementation of the virtual signal generator circuit. As depicted therein, a first three time incremented signal passages through the first virtual signal generator (n=l) results in the construction of the first output signal o(t)' . In the fourth sample period, this interim output signal o(t)' is fed to the modulation circuit 38 to become the self- modulation signal 60 that is fed back to the angle generator 28, and the ultimate output signal o(t), is constructed by the wave constructor 34 and output to the accumulator 18. The output signal o(t), is not then fed back to the modulator 38 to become the modulation signal 62. Thereafter, in a fifth sample period the signal generator circuit, acting now as the second signal generator (n=2) creates the output signal 0(t) ₂ through the angle generator 28, sine logic 30, envelope generator 32 and wave constructor 34 components, and the output signal o(t) ₂ is fed to the accumulator 18. A modulation step utilizing modulator 38 is not undertaken in this (n=2) time multiplexed circuit configuration. It is therefore to be understood that Fig. 9 depicts the synthesizer engine circuit 16, time multiplexed for n=l and n=2 and utilized in a parallel circuitry configuration.

What I claim is: