CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit and priority of U.S. Provisional Application Serial Number 63/131,268, filed on December 28, 2020, which is hereby incorporated by reference herein, including all references and appendices cited therein, for all purposes as if fully set forth herein. This application is related to U.S.

Application Serial Number X, filed on X, Attorney Docket No. 9861US/9861/AIRA, entitled "MULTI-BIT FEEDBACK PROTOCOL SYSTEMS AND METHODS," which is hereby incorporated by reference herein, including all references and appendices cited therein, for all purposes as if fully set forth herein.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0002] The methods and systems disclosed herein pertain to telecommunications, and more specifically, but not by way of limitation, to transmission of messages and the correction of errors in those messages in a variety of ways. Some of these methods can include the use of one or more types of indexing associated with feedback to correct errors in messages exchanged between two end points.

SUMMARY

[0003] According to some embodiments, the present disclosure is directed to a method comprising determining error correction for a received packet having errors, generating an index of the error correction, the index comprising error positions for the errors in the received packet, and transmitting the index to a receiver decoder.

[0004] According to some embodiments, the present disclosure is directed to a method comprising transmitting a packet to a receiver over a channel having noise that causes the packet to be received with errors, providing a first round of error correction in response to the errors by source encoding and channel encoding an error vector of the errors as an index, and transmitting the index to the receiver.

[0005] According to some embodiments, the present disclosure is directed to a system comprising a transmitter encoder comprising a processor, the processor executing instructions to determine error correction for a received packet having errors, and generate an index of the error correction, the index comprising error positions for the errors in the received packet, and a receiver decoder comprising a processor, the processor executing instructions to deindex the index to identify the error positions, and correct the errors in the received packet using the error positions to generate a corrected packet.

[0006] According to some embodiments, the present disclosure is directed to a method comprising transmitting an original packet on an asymmetric link, the asymmetric link being a communication channel where available transmission power is not equal for both the transmitter and the receiver; receiving a received packet by a transmitter encoder; conducting a first round of error correction that comprises: generating an index of the error correction, the index comprising error positions for the errors; and transmitting the index on the forward link; conducting one or more additional rounds of error correction, each of the one or more additional rounds of error correction comprising: determining an error correction for errors in a corrected packet; generating an index of the error correction, the index comprising error positions for the errors; transmitting the index on the forward link; deindexing the index to identify the error positions; and correcting the errors in the received packet using the error positions to generate an additional corrected packet, wherein each round of the one or more additional rounds of error correction generates a new corrected packet.

BRIEF DESCRIPTION OF DRAWINGS

[0007] Exemplary embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements.

[0008] FIG. 1 is an example architecture where aspects of the present disclosure can be practiced,, in combination with an example signal flow.

[0009] FIG. 2 is a signal flow diagram of an example indexing error correction method.

[0010] FIG. 3 is a schematic representation of a source and channel encoding/ decoding process.

[00'11] FIG. 4 is a schematic signal flow diagram of the present disclosure.

[0012] FIG. 5 is a flow of an example indexing process of the present disclosure.

[0013] FIG. 6 schematically illustrates an example combinatorial optimization method for use in conjunction with a telescopic indexing method.

[0014] FIG. 7 is a schematic and flow diagram of an example architecture or environment.

[0015] FIGS. 8 and 9 are both graphs of data packet transmission efficiency improvement using indexing as described tierein.

[0016] FIG. 10 is a flowchart of an example method of the present disclosure.

[0017] FIG. 11 is a flowchart of another example method of the present disclosure.

[0018] FIG. 12 is a schematic diagram of an example computer system that can be used to implement aspects of the present disclosure. DETAILED DESCRIPTION

Overview

[0019] Wireless communication requires sending information packets from the transmitter (Tx) to the receiver (Rx) without error. Even with strong error correction codes, the packet could be corrupted. Currently wireless protocol uses error detecting codes and retransmission schemes to protect the packet's integrity. An example method of error correction is referred to as cyclic redundancy check (CRC). CRC is the most- widely-used short error-detecting code to detect accidental payload changes. CRC is computed on the payload at the Tx, and attached to the end of the payload. Both payload and CRC are transmitted to Rx. At the receiver, the received CRC is compared to the CRC computed by the received payload.

[0020] If the received CRC equals the computed CRC, the CRC passes. If the received CRC doesn't match the computed CRC, the CRC fails. When CRC passes, it is of very high probability that the packet is not contaminated, so ACK is sent to the transmitter side, to signal the transmitter to continue to transmit the next packet. When CRC fails, it is of very high probability that the packet is contaminated, so NACK is triggered, to ask the transmitter for retransmission. There is some probability that the ACK/NACK is not received by the Tx side. Then after a timeout, Tx will re-transmit the packet.

[0021] In some instances, even 1-bit of error causes full retransmission of the data packet. The feedback is one-bit information of whether the packet is received correctly or not, that is exactly one bit information (timeout is also a bit of information or packet not received correctly). Overall, with single-bit information feedback from Rx to Tx, the Tx cannot do anything other than re-transmitting the whole packet. When the received packet has only a one to a few bits of error, it is not efficient to retransmit the whole packet again. Example Embodiments

[0022] Referring now to FIGS. 1 and 2 collectively, which illustrate an example architecture and signal flow where aspects of the present disclosure are implemented. In more detail, FIG. 1 is a schematic signal flow of an example full feedback approach. In this example, the Tx 102 can transmit an original message 104 to the Rx 106 on a channel/forward link 108 that may be noisy and produce errors in the packet. Thus, in this example, only the channel/forward link 108 is noisy.

[0023] The Rx 106 detects errors using CRC or an equivalent method. The Rx 106 transmits feedback to the Tx 102 that comprises an Rx decoded packet. The Rx decoded packet is transmitted as feedback to Tx 104 on a noiseless link or channel 110. It will be understood that the noiseless reverse link is achieved in practice because (1) one device on the link, such as the Rx 106, transmits at higher power or (2) one device on the link, such as the Rx 106, uses a more robust modulation/coding scheme. To be sure, the forward Link is the channel used by the Tx 102 to transmit the original message to the Rx 106.

[0024] When the Tx 102 receives decoded packet from the Rx 106, the kx 102 determines a difference between the original message and what Rx 102 received and generates an error vector 112. In the next round, the Tx 102 transmits the error vector 112 to the Rx 102, rather than the original message. Tx 104 can perform packet correction with the received error vector 112 and the original/received message 104. [0025] If the CRC computed by the Rx 106 on the corrected message passes, the Rx 102 will feedback an ACK to Tx 104, and the w ^T hole process converges. Tire Tx 104 transmits the next packet. If the CRC does not pass, the Rx 102 will feedback a NACK to Tx 104 along with the corrected message. Another error vector can be calculated by the Tx 102 and reused as described above. This iterative process can be performed in multiple rounds until a retransmission threshold is encountered. The retransmission threshold corresponds to a maximum number of rounds of error correction that can be attempted before failure is declared. When failure is declared by the Tx 102, the Tx 102 can start transmitting a next packet. The retransmission threshold is configurable and can be selected according to network design requirements.

[0026] Referring now to FIGS. 1 and 2 collectively, it will be understood that a feedback phase as described above can be divided into two portions, a source coding and a channel coding. The example indexing methods disclosed herein belong to the source coding portion. Source coding is a compression procedure for error vectors. [0027] It will be understood that error vectors are typically sparse, and can be further compressed to a much shorter representation. The compressed representation can be heavily coded to avoid corruption via channel coding/'encoding, and most of the time, even with heavy channel coding, the coded compressed representation is still much shorter than the original message, which could lead to improved efficiency and reliability.

[0028] An example process that can be used to compress error vectors involves error position indexing, which is diagrammatically illustrated in FIG. 2. The error position indexing/de-indexing approach can be used for cornpressing an error vector. The indexing method can be used to send an index of error positions. In the example of FIG.

2, an error position indexing source coding method may involve single bit indexing. An indexed code can be represented with three bits, to send an error vector of seven bits. Thus, the example of FIG. 2 illustrates the indexing method for a block of length N(N=7), where each error position requires ceiling(log(N)) bits. As N becomes larger, and the error vector is sparse, then the indexing method can save a significant amount of energy-per-bit. Referring back to FIG. 1, the Tx 102 can create an index 1 14 of the error correction and then create coded indexes 116, which are compressed representations of indexes.

[0029] Deindexing is the reverse operation of indexing, by reconstructing the error vector by the received indexed code at Rx side. Hie error vector can be noise tolerant and can be reconstructed correctly and without error assuming when the underlying channel code is applied.

[0030] FIG. 3 is a schematic diagram of an example flow. FIG. 4 is a schematic signal flow diagram. The following descriptions will reference both FIGs. 3 and 4 collectively. An encoder 402 can transmit an original message U across a channel (e.g., any communications link) 404 to a decoder 406. In one example, the message U has a size of 100 bits. The message U is received in error resulting in an erroneous message U + e ₁ . That is, there are error bits e ₁ present in the original message U. This erroneous message U + e ₁ can be used as feedback. Using the entire erroneous message U + e ₁ as feedback creates transmission overhead due to the size of the erroneous message U + ey which includes the original 100 bits of the message U with its error bits e ₁ .

[0031] In some embodiments, the encoder 402 can compare the original message U with the erroneous message U + e ₁ to determine the error bits That is, the U + is compared with the original message U to identify the error bits e ₁ . These error bits e ₁ can be indexed to create an index E ₁ . The index Ei can be transmitted and de-indexed by the decoder 406. A recovered message U' can be recovered in an XOR process 408. CRC can be computed on the recovered message U', if the CRC passes the process terminates. If no errors are present, the process ends as the original message U has been correctly received. Otherwise, the process repeats using the feedback of U+ e ₂ . and index E ₂ . This process can iterate until the original message is recovered with no errors or an indexing threshold is reached. For example, the process can be allowed to iterate five times (or any other number of rounds). If errors are still found after reaching the indexing threshold the message can be accepted as-is with errors. If there is no tolerance for errors (and the threshold has been reached) in the communications process the flow may terminate and the encoder or decoder may transmit a warning message or terminate communications. [0032] An example indexing procedure is illustrated in FIG. 5, which is a schematic signal flow diagram. The error bits e ₁ are illustrated as being a part of the original message U. That is, the error bits eq are illustrated as being dispersed throughout U, which is why this construct may be referred to as a sparse index. The locations of the errors are noted as 11, 12, and 13. By way of example, out of 100 bits of the message U, a first error at location 11 may be at position 5, a second error at location 12 may be at position 20, and a third error at location 13 may be at position 95. Hie selection of these locations and bits is arbitrary and provided for descriptive purposes only. Each error location requires 7 bits to uniquely identify (log2(100)). So a total bitspace size of the error bits e ₁ is 21 bits. Thus, instead of transmitting a 100 bit error message as feedback, an index El having a size of 21 bits is transmitted.

[0033] Referring now to FIGS. 4 and 5 collectively, errors may be introduced when transmitting or decoding the index E1. For example, the error corrections associated with the location 11 and the location 13 may have been received correctly, but error correction associated with location 12 were received in error. For example, the error correction of location 12 was incorrectly identified as belonging to location 50 instead of location 20. Haus, if corrected, an updated message IT would have the proper corrections for locations 11 and 13, but when a comparison is performed for the updated message U' would include not only the original error associated with location 12, but now in a fourth location 14. That is, the updated message U' has errors at position 20 (because it was never corrected) and at position 50 (the new error).

[0034] The process illustrated in FIG. 3 proceeds where new error bits e ₂ are discovered in the updated message U'. These new error bits e ₂ are converted into an index E2. This index can be de-indexed to recover the new error bits e ₂ and correct the updated message U ^' . Again, if the errors in the updated message U ^' are gone, the process can terminate. Otherwise, another round of feedback and error correcting can occur. Collectively, the processes illustrated in FIGS. 3-5 are referred to generally as simple indexing.

[0035] Rather than using iterative processes that involve evaluating updated messages as feed back, another process referred to as telescopic indexing can be used. In general, telescopic indexing allows for errors in correction messages to be identified and remedied. Referring now to RIGS. 4 and 7 collectively, in an initial flow, the encoder 402 transmits an original message U to a decoder 406. Errors may be introduced into the original message U that results in an erroneous message being received erroneous message U + e ₁ . The encoder 402 can compare the erroneous message U + e ₁ the original message U to determine the error bits e ₁ . These error bits e ₁ can be indexed as El and transmitted to the decoder 406. Assuming no additional errors have been introduced into the index El the error bits e ₁ can be used to correctly decode the original message U.

[0036] An erroneous index is created when an error is introduced into the index El (could be introduced during transmission, receipt, or deindexing). Hie decoder 146 can deindex the index but instead of recovering error bits rx the decoder 406 recovers error bits illustrated as a correction. Instead of feeding back the updated message U', the received correction is used for feedback. The encoder 402 can compare the transmitted index bits with the received index bits el ₁ to identify discrepancies. . If discrepancies are identified, the encoder 402 can correct these errors in the error bits G . Once all errors have been fixed, the various iterations of corrections such as the correction with error bits e ₁ and the correction with error bits are processing using an XOR function (see FIG. 4) to recover the original message U. [0037] In sum, after the initial process of comparing a received message to the original message U to identify errors, any further error correction will occur by comparing versions of corrections to identify errors. Once the correction has been perfected the original message U can be recovered. [0038] As noted above, one advantage of transmitting an index rather than an entire errant message as feedback is that this reduces transmission bandwidth requirement from 100 bits (as an example) to the index space, which is only a subset of the 100 bits. In the example given above the index had a bit size of 21 bits. In some instances, the index can be further reduced in size by optimizing the index through combinatorial optimization. For example, locations 11, 12, and 13 have individual bit sizes of 7 bits for a total of 21 bits. This same bitspace can be represented as 18 bits using combinatorial optimization as depicted in FIG. 6. The indexed binary representation El can be searched across a combinatorial space 600 to create a combinatorial optimized index

[0039] FIG. 7 is a schematic diagram of an example environment where aspects of the present disclosure can be practiced. The environment illustrates implementation of a multi-bit feedback system which provides improved communication efficiency. A multi-bit feedback system can feed back more than one-bit information and enables the Tx side to transmit information more efficiently (beyond just retransmission).

[0040] In this example, a first endpoint device such as an Internet-of-Thlngs (loT) sensor 702 (example Tx) can communicate with a second endpoint device, such as a Smartphone 704 (example Rx). Example use cases involving these devices are for descriptive purposes and are not intended to be limiting. In this embodiment, the sensor 702 is the transmitter (encoder) and the Smartphone 704 is a receiver (decoder). These roles can be reversed as necessary. In this example, a message 706 is transmitted from sensor 702 to Smartphone 704. Smartphone 704 returns feedback, which is processed by a feedback encoder 708 to produce a correction 710 that is transmitted to the Smartphone 704. The Smartphone 704 uses a feedback decoder 712 to process the original message and the correction. An ACK 714 message is transmitted from the Smartphone 704 to the sensor 702 when the message is corrected and matches the original message. [0041] For context, loT devices may include sensors, whose major functionality is to transmit sensor data to a host. loT devices are typically power constrained, and the host is not power constrained and can use higher transmission power. Thus, a forward channel may be noisier than a feedback channel. This discrepancy is termed an asymmetric channel condition. When asymmetric channel conditions exist, it can be assumed that the Rx can send back information to Tx without error, while the Tx's information sent to Tx may be noisy. In some instances, an asymmetric link is a communication channel where available transmission power is not equal for both the transmitter and the receiver. For example, an asymmetry may exist when one device is a sensor and another device is a Smartphone. The smartphone will likely always have more power than a sensor. In another example, one device can include a base station, such as a cellphone transmitter. A second device using the link would be a Smartphone. In this example, a base station will likely always have more power. Additionally, an asymmetry may exist where one device has a more robust modulating/encoding scheme.

[0042] FIG. 8 is a graphical representation packet error rate versus attenuation. A shift in attenuation curve from a baseline (no error correction) 802, relative to indexing- based feedback 804 is shown. In this example, three rounds of error correction are used. As can be seen, when indexing-based feedback is used, packets can be successfully transmitted even when higher attenuation levels are experienced in the channel/link. FIG. 9 is a graphical representation of the shift in attenuation curve when ten rounds of error correction are used. To be sure, as more rounds of error correction are used, a corresponding increase in attenuation mitigation or response is achieved.

[0043] FIG. 10 is a flowchart of an example method. The method can involve the use of an asymmetric link that produces noise in packets transmitted on a forward link between a transmitter to a receiver, and no noise on a reverse link from the receiver to the transmitter. [0044] The method can include a step 1002 of transmitting an original packet on a forward link from a transmitter to a receiver. As noted above, noise in the forward link may create errors in the original packet when it is received by the receiver decoder.

[0045] The method can include a step 1004 of receiving,, by the transmitter encoder, a received packet that comprises errors. Hie method includes an iterative or cyclic error correction process that can involve one or more rounds of error correction. A first round of error correction can comprise a step 1006 of generating an index of the error correction, the index comprising error positions for the errors. The method also includes a step 1008 of transmitting the index on the forward Link. The method can include a step 1010 of generating a corrected packet using the index. This can include deindexing the index and correcting the error bits. Again, the index indicates the location of bits that require flipping. The receiver decoder can flip bits in the received packet according to the error positions in the index to generate the corrected packet. [0046] The method can include a step 1012 of receiving, by the transmitter encoder, the corrected packet and determining if errors are present. If no errors are present, the method terminates. If errors are present, the method can include a process of conducting one or more additional rounds of error correction. Each round can include a step 1014 of determining an error correction for errors in a corrected packet, as well as a step 1016 of generating an index of the error correction, the index comprising error positions for the errors. In some embodiments, the method includes a step 1018 of transmitting the index on the forward link and a step 1020 of deindexing the index to identify the error positions. In some embodiments, the method can include a step 1022 of correcting the errors in the received packet using the error positions to generate an additional corrected packet. It will be understood that each round of the one or more additional rounds of error correction generates a new corrected packet that can be compared to the original packet to determine if errors are or are not present. [0047] FIG. 11 is a flowchart of another example method. The method can include a step 1102 of determining error correction for a received packet having errors. This can include identifying bits that are erroneous. Next, the method can include a step 1104 of generating an index of the error correction. As noted above,, the index comprises error positions for the errors in the received packet. The index can be a sparse index that can be optimized through compression. Next, the method includes a step 1306 of transmitting the index to a receiver decoder.

[0048] In various embodiments, the method can include as step 1108 of deindexing the index to identify the error positions, along with a step 1 1 10 of correcting the errors in the received packet using the error positions to generate a corrected packet. The method can also include steps such as performing one or more additional rounds of error correction by comparing the corrected packet to an original packet, and generating another error correction and another index when errors are identified in the comparison.

[0049] In various instances, the one or more additional rounds of error correction terminate when a retransmission threshold is reached. The method can include transmitting a new packet when the retransmission threshold is reached or when a corrected packet corresponds to the original packet.

[0050] FIG. 12 is a diagrammatic representation of an example machine in the form of a computer system 1, within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In various example embodiments, the machine operates as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine may operate in the capacity of a server or a client machine in a server-client network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be an Internet-of-Things (loT) device or system, personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA)., a cellular telephone, a portable music player (e.g., a portable hard drive audio device such as a Moving Picture Experts Group Audio Layer 3 (MP3) player), a web appliance, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0051] The computer system 1 includes a processor or multiple processor(s) 5 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), or both), and a main memory 10 and static memory 15, which communicate with each other via a bus 20. The computer system 1 may further include a video display 35 (e.g., a liquid crystal display (LCD)). The computer system 1 may also include an alpha-numeric input device(s) 30 (e.g., a keyboard), a cursor control device (e.g., a mouse), a voice recognition or biometric verification unit (not shown), a drive unit 37 (also referred to as disk drive unit), a signal generation device 40 (e.g., a speaker), and a network interface device 45. The computer system 1 may further include a data encryption module (not shown) to encrypt data.

[0052] The drive unit 37 includes a computer or machine-readable medium 50 on which is stored one or more sets of instructions and data structures (e.g., instructions 55) embodying or utilizing any one or more of the methodologies or functions described herein. The instructions 55 may also reside, completely or at least partially, within the main memory 10 and/or within the processor(s) 5 during execution thereof by the computer system 1. The main memory 10 and the processor(s) 5 may also constitute machine-readable media.

[0053] The instructions 55 may further be transmitted or received over a network via the network interface device 45 utilizing any one of a number of well-known transfer protocols (e.g., Hyper Text Transfer Protocol (HITP)). While the machine-readable medium 50 is shown in an example embodiment to be a single medium, the term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database and/or associated caches and servers) that store the one or more sets of instructions. The term "computer-readable medium" shall also be taken to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by the machine and that causes the machine to perform any one or more of the methodologies of the present application, or that is capable of storing, encoding, or carrying data structures utilized by or associated with such a set of instructions. The term "computer-readable medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical and magnetic media, and carrier wave signals. Such media may also include, without limitation, hard disks, floppy disks, flash memory cards, digital video disks, random access memory (RAM), read only memory (ROM), and the like. The example embodiments described herein may be implemented in an operating environment comprising software installed on a computer, in hardware, or in a combination of software and hardware.

[0054] One skilled in the art will recognize that the Internet service may be configured to provide Internet access to one or more computing devices that are coupled to the Internet service, and that the computing devices may include one or more processors, buses, memory devices, display devices, input/output devices, and the like. Furthermore, those skilled in the art may appreciate that the Internet service may be coupled to one or more databases, repositories, servers, and the like, which may be utilized in order to implement any of the embodiments of the disclosure as described herein.

[0055] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present technology has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the present technology in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the present technology. Exemplary embodiments were chosen and described in order to best explain the principles of the present technology and its practical application, and to enable others of ordinary skill in the art to understand the present technology for various embodiments with various modifications as are suited to the particular use contemplated.

[0056] If any disclosures are incorporated herein by reference and such incorporated disclosures conflict in part and/or in whole with the present disclosure, then to the extent of conflict, and/or broader disclosure, and/or broader definition of terms, the present disclosure controls. If such incorporated disclosures conflict in part and/or in whole with one another, then to the extent of conflict, the later-dated disclosure controls.

[0057] Aspects of the present technology are described above with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present technology. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. [0058] In this description,, for purposes of explanation and not limitation,, specific details are set forth, such as particular embodiments, procedures, techniques, etc. in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details.

[0059] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" or "according to one embodiment" (or other phrases having similar import) at various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Furthermore, depending on the context of discussion herein, a singular term may include its plural forms and a plural term may include its singular form. Similarly, a hyphenated term (e.g., "on-demand") may be occasionally interchangeably used with its non-hyphenated version (e.g., "on demand"), a capitalized entry (e.g., "Software") may be interchangeably used with its non-capitalized version (e.g., "software"), a plural term may be indicated with or without an apostrophe (e.g., PE's or PEs), and an italicized term (e.g., "N+l") may be interchangeably used with its non-italicized version (e.g., "N+l"). Such occasional interchangeable uses shall not be considered inconsistent with each other.

[0060] Also, some embodiments may be described in terms of '"means for" performing a task or set of tasks. It will be understood that a "means for" may be expressed herein in terms of a structure, such as a processor, a memory, an I/O device such as a camera, or combinations thereof. Alternatively, the "means for" may include an algorithm that is descriptive of a function or method step, w ^T hile in yet other embodiments the "means for" is expressed in terms of a mathematical formula, prose, or as a flow chart or signal diagram.