Title:
INFORMATION PROCESSING DEVICE AND DATA TRANSFER METHOD
Document Type and Number:
WIPO Patent Application WO/2011/033862
Kind Code:
A1
Abstract:
Provided is an information processing device, wherein the time required and power consumed in having a cache memory search for an address array can be reduced, when transferring elements to the cache memory. The processing device, which transfers m pieces of elements having a predetermined line-up order, to a cache memory comprising n pieces of memory banks, is comprised of: a storage unit wherein the m pieces of elements are stored in the n pieces of register banks, by being interleaved in the lined-up order thereof; a control unit that calculates the processing size by dividing the block size within the memory banks by the stride, and makes an assessment of whether the starting address matches either of the forefront addresses of the blocks. The processing device is also comprised of a processing unit that divides the m pieces of elements into processing groups consisting of elements in continuous line-up order, and consisting of a number of elements that has the processing size multiplied by n, and that, when the starting address matches the forefront address, reads out the elements in parallel from each of the register banks and transfers the elements, in such a way that elements are read out in parallel from each of the block data, which has the elements within the processing group divided by the processing size, in the lined-up order of the elements.
Inventors:
KANOH YASUSHI (JP)
Application Number:
PCT/JP2010/062664
Publication Date:
March 24, 2011
Filing Date:
July 28, 2010
Export Citation:
Assignee:
NEC CORP (JP)
KANOH YASUSHI (JP)
KANOH YASUSHI (JP)
International Classes:
G06F12/08; G06F15/167; G06F17/16
Foreign References:
| JP2008250926A | 2008-10-16 | |||
| JP4060960B2 | 2008-03-12 | |||
| JP3005456B2 | 2000-01-31 | |||
| JP2878256B1 | 1999-04-05 |
Attorney, Agent or Firm:
MIYAZAKI, Teruo et al. (JP)
Akio Miyazaki (JP)
Akio Miyazaki (JP)
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