The present invention relates to an initial synchronization device used in a mobile of a cellular telecommunication system, for identifying the frame boundary and which of a plurality of pre-defined complex valued SYNC-DL sequences is used so as to search for a cell, comprising a coefficient-reloadable matched filter means. Furthermore, the present invention relates to an initial synchronization method used in a mobile of a cellular telecommunication system, for identifying the frame boundary and which of a plurality of pre-defined complex valued SYNC-DL sequences is used so as to search for a cell.

Preferably, such a device and such a method is used in a Time Division Synchronous Code Division Multiple Access (TD-SCDMA) system which is the Chinese contribution to the international family of Mobile Radio Systems for the 3rd Generation services of UMTS (Universal Mobile Telecommunications System) and IMT 2000 (International Mobile Telecommunications) and has been approved as a low chip rate time division duplex (TDD) option in the 3rd Generation Partnership Project (3GPP).

In a cellular telecommunication system, during an initial cell search, where the user equipment (UE) searches for a cell, the UE uses the SYNC-DL in the Downlink Pilot Time Slot (DwPTS) to acquire DwPTS synchronization to a cell. There are a plurality of, preferably 32, complex valued SYNC-DL sequences defined in the system. The UE needs to identify the frame boundary and which of the plurality of possible SYNC-DL sequences is used. The search for DwPTS is very challenging. The reason is that due to the high number of complexed valued SYNC-DL sequences each of which has a rather high length and due to the high length of a sub-frame it takes a very long time to search all the SYNC-DL sequences on all the high plurality of possible phases. If there is an analogue/digital conversion resulting in a duplication of the analogue/digital sample rate, the possible phases will double.

The DwPTS synchronization is typically done with one or more matched filters or any similar device (s) matched to the received SYNC-DL. There are usually two ways to accomplish the initial synchronization: One is to use matched filter to calculate parallelly, and the other is to use a correlator to calculate serially, wherein it takes a tremendous time for the correlator to search all the possible conditions. Even if a matched filter is used, it will take a rather long time to scan all the plurality of possible SYNC-DL

sequences. Since the provision of a complex multiplier is required, it takes huge resources to implement such a coefficient re-loadable complex matched filter.

DE 198 44139 A1 discloses an apparatus and a method for carrying out a complex multiplication using an adder, a subtractor, two negation units, a result selection unit, two multipliers, EX-OR gates and an output unit. The adder creates a sum and the subtractor creates a difference of the real and the imaginary part of the output from the first multiplier. The first negation unit performs a negation of the sum according to the real part of the output of the second multiplier. A second negation unit performs a random negation of the difference depending on the imaginary part of the second multiplier. The result selection unit selects the result from the two negation units either as imaginary part and real part or as real part and imaginary part of the complex multiplication result. The selection is made dependent on the real part and imaginary part of the second multiplier. The output signals of the two negation units are cross-fed as inputs of the two multipliers. The EX-OR gates create a selection control signal corresponding to an XOR connection of the real part and the imaginary part of the second multiplier.

US 5,500, 811 A describes a compact Finite Impulse Response (FIR) filter using one or both of a compact address sequencer and a compact multiplier/accumulator. The address sequencer exploits certain symmetry properties existing between different phases of a polyphase FIR filter in order to reduce coefficient storage and simplify address sequencing.

The multiplier/accumulator is capable of performing two multiply/accumulate operations per clock cycle, avoiding in certain instances the need to add a second multiplier/accumulator.

The area required to realize a FIR filter for performing real-time filter is therefore reduced.

DE 44 42 959 A1 discloses a complex number multiplier monolithic integrated circuit for serial data which circuit comprises two multiplexers, a complimenter and a delay element. The signal input is connected to the first multiplexer and the complimenter. The complimenter is connected to the second multiplexer. The output signal from the first multiplexer is routed to the delay element, and the output from the delay element is routed to the input of the second multiplexer.

In US 4,927, 775, it is described an apparatus for the cross-correlation of two complex sampled digital data signals X and Y, which apparatus uses a first N-stage CORDIC rotator of pipeline sequential form for rotating each of the real and imaginary data portions of the first (X) complex sampled signal sequentially through a summation of angles 8

where t 1 or-1, all and c-2=tan'\2'") for n=0, 1,2, 3,... N-2) until Xl,,, is approximately zero and a substantially zero phase angle is reached. The sign from each i-th stage of this first pipeline is also utilized to determine the sign of rotation in each like- positioned i-th stage of a plurality M of additional CORDIC pipeline rotators, where M is the total number of time delays at which the cross-correlation function is evaluated. The real and imaginary portions of the complete M-th interval cross-correlation product are each obtained by multiplying the associated complex output of each of the Y pipeline rotators by the first pipeline magnitude signal output. N samples are then summed to provide at the j-th rotator output the appropriate pair of the real and imaginary parts of the j-th complex digital data output sample.

An object of the present invention is to improve the efficiency of the initial synchronization.

In order to achieve the above and further objects, according to a first aspect of the present invention, there is provided an initial synchronization device used in a mobile of a cellular telecommunication system, for identifying the frame boundary and which of a plurality of pre-defined complex valued SYNC-DL sequences is used so as to search for a cell, comprising a coefficient re-loadable match filter means, characterized in that said coefficient re-loadable match filter means is adapted to operate in a pipeline mode.

According to a second aspect of the present invention there is provided an initial synchronization method used in a mobile of a cellular telecommunication system, for identifying the frame boundary and which of a plurality of pre-defined complex valued SYNC-DL sequences is used so as to search for a cell, characterized by the step of operating a coefficient re-loadable match filter means in a pipeline mode.

So, the present invention provides the use of a coefficient-re-loadable matched filter means working in a pipeline mode without complex multiplying, and, thus, a high efficient implementation architecture of a searcher without any complex multiplier. The architecture proposed by the present invention can search all the phases of all the possible SYNC-DL sequences in a rather short time so that the speed of the initial synchronization can be increased over the prior art. Namely, if the algorithm of the synchronization is multicycle detection or singlecycle detection with multicycle verification, by using the architecture according to the present invention, the search time of every cycle can be greatly reduced.

Further advantageous embodiments are defined in the dependent claims.

In particular, a predetermined number of SYNC-DL sequences having predefined values can be generated and/or stored.

In a further preferred embodiment of the present invention, in particular suitable for a TD-SCDMA system, wherein a complex multiplication of sampled data of a data stream of a received signal, in particular with a sample rate being half a chip, with a plurality of, in particular 32, complex valued SYNC-DL sequences is performed, wherein said multiplication comprises a multiplex operation on the sampled data in accordance with the SYNC-DL sequences and an accumulation of the output data of said multiplexing. So, a parallel multiplication is realized by this embodiment in a simple manner.

The multiplexing means used may comprise group (s) of four multiplexing means with a first multiplexing means dealing with the phase rotation of +j, a second multiplexing means dealing with the phase rotation of-1, a third multiplexing means dealing with the phase rotation of j, and a fourth multiplexing means dealing with the phase rotation of+1.

Preferably, two-select-one multiplexers should be used.

Moreover, each multiplexing means may comprise a first multiplexer for the real part of the complex input, a second multiplexer for the imaginary part of the complex input, a first inverter and a second inverter, wherein in particular the output of the first multi- plexer may be delayed by a first delay means, and the output of the second multiplexer may be delayed by a second delay means.

In a still further preferred embodiment of the present invention, the accumulation is carried out in cascade configuration including a plurality of stages, wherein the results of each stage may be registered, and at each stage two results of the preceding stage may be added and a sum may be outputted as a result of the respective stage.

In a still further preferred embodiment of the present invention, the energy of the final result outputted by the accumulation may be calculated and compared with a predetermined threshold, wherein a chip counting means and a SYNC-DL code number counting means is held up if the energy exceeds the threshold.

The above-described objects and other aspects of the present invention will be better understood by the following description and the accompanying figures.

A preferred embodiment of the present invention will be described with reference to the drawings in which:

Fig. 1 schematically shows the frame structure of the physical channels in a TD-SCDMA system; Fig. 2 schematically shows the architecture of an initial synchronization apparatus according to a preferred embodiment of the present invention; and Fig. 3 schematically shows the architecture of the multiplexers provided in the apparatus of Fig. 2.

TD-SCDMA (Time Division Synchronous Code Division Multiple Access) is the Chinese contribution to the international family of Mobile Radio Systems for the 3rd Generation services of UMTS (Universal Mobile Telecommunications System) and IMT 2000 (International Mobile Telecommunications). It has been approved as the low chip rate TDD (Time Division Duplex) option in 3GPP.

The chip rate of a TD-SCDMA system is 1.28 Mcps. The frame structure of the physical channels in the TD-SCDMA system is illustrated in Fig. 1. The period of a subframe is 5ms, and it is divided into 7 timeslots, 2 pilot timeslots and 1 guard period. Each timeslot contains two data parts, between which there is a mid-amble sequence. The mid- amble is actually a training sequence designed for channel estimation. Every slot ends with a guard period.

During the initial cell search, the UE (User Equipment) searches for a cell. The initial cell search is carried out in four steps.

During the first step of the initial cell search procedure, the UE uses the SYNC-DL (Synchronization Downlink) in DwPTS (Downlink Pilot Time Slot) to acquire DwPTS synchronization to a cell. The subframe length is 6400 chips. There are 32 complex valued SYNC-DL sequences defined in the system. The UE needs to identify the frame boundary and which of the 32 possible SYNC-DL sequences is used.

During the second step of the initial cell search procedure, the UE receives the mid-amble of the P-CCPCH (Primary Common Control Physical Channel). Since the SYNC- DL and the group of basic mid-amble codes of the P-CCPCH are related one by one (i. e., once the SYNC-DL is detected, the four mid-amble codes can be determined), the UE knows which four basic mid-amble codes are used. Then the UE can determine the used basic mid- amble code using a try and error technique. The same basic mid-amble code will be used throughout the frame. As each basic mid-amble code is associated with a scrambling code, the scrambling code is also known by that time.

During the third step of the initial cell search procedure, the UE searches for the MIB (Master Indication Block) of a multi-frame of the BCH (Broadcast Channel) in the P-CCPCH indicated by QPSK (Quadrature Phase Shift Keying) phase modulation of the DwPTS with respect to the P-CCPCH mid-amble. The control multi-frame is positioned by a sequence of QPSK symbols modulated on the DwPTS. Four consecutive DwPTSs are sufficient for detecting the current position in the control multi-frame.

During the fourth step of the initial cell search procedure, the broadcast information of the found cell in one or several BCHs is read.

It is regarded that the first step of the initial cell search procedure is the most challenging. The reason is that there are totally 32 complex valued SYNC-DL sequences (64 chips long) possible and the length of a sub-frame is 6400 chips. Apparently, it takes a very long time to search all the 32 SYNC-DL sequences on all the 6400 possible phases. If the analogue/digital sample rate doubles, the possible phases will double.

The DwPTS synchronization is typically done with one or more matched filters (or any similar device) matched to the received SYNC-DL. There are usually two ways to accomplish the initial synchronization. One is to use a matched filter to calculate parallely, the other is to use a correlator to calculate serially. Of course, it will take a tremendous time for the correlator to search all the possible conditions. Even if a matched filter is used, it will at least take 5*32=160 ms to scan all the 32 possible SYNC-DL sequences. And it takes huge resources to implement such a coefficient re-loadable complex matched filter.

Fig. 2 schematically shows the architecture of an initial synchronization apparatus according to a preferred embodiment of the present invention which can search all the phases of all the possible SYNC-DL sequences in only 5ms. If the algorithm of the synchronization is multicycle detection or singlecycle detection with multicycle verification, by using the architecture proposed, the search time of every cycle could be greatly reduced.

General speaking, it is a coefficient re-loadable matched filter without complex multiplier working in a pipeline mode.

The chip rate of a TD-SCDMA system is 1.28 Mcps, and it is presumed that the sample rate is 1/2chip. In order to use the hardware most efficiently, the matched filter works at a frequency of 2*1. 28*32=81. 92 MHz. In this way, it can process all the 32 possible SYNC-DL sequences in a half chip.

The process of the synchronization by using the apparatus shown in Fig. 2 is described as follows.

Firstly, the sampled stream which is complex valued is fed into a shift register.

Because the sample rate is 1/2 chip and the sampled data is complex valued, the length of the shift register is 64*2=128 and the width is 6*2=12 bits.

During each l/2 chip, 32 basic SYNC-DL sequences are read out from a ROM at the frequency of 81.92 MHz. The predefined basic SYNC-DL sequences are stored in a ROM, which is configured as 32*63 bits. So, one of the basic SYNC-DL (64 chips long) could be read out in one clock (81. 92 MHz). This ensures that all the 32 possible basic SYNC-DL sequences can be read out in 1/2chip.

During each clock, the sampled data is complex multiplied with the SYNC-DL (complex rotated from the basic SYNC-DL). The complex multiplication is simplified to a multiplexing operation. A basic SYNC-DL (binary valued) is first mapped to a real valued sequence and then rotated-n/2 each chip to generate the complex valued SYNC-DL. The MUXs are devided into four patterns: MUX1 deals with the phase rotation of +j, MUX2 deals with the phase rotation of-1, MUX3 deals with the phase rotation of -j and MUX4 deals with the phase rotation of +1. The mapping from binary to real and complex rotation process is shown in table 1. Because the SYNC-DL should be complex conjugated before being correlated with the received signal, the actually used multiplication factor is calculated in the right part of every cell. For example, the equivalent multiplication factor of MUX1 is either j or +j, which is determined by the current SYNC-DL binary bit. The other three cases are induced in the same way.

Table 1. Mapping & complex rotation Rotation J-1 j 1 Binary bit Complex MUX1 MUX2 MUX3 MUX4 symbol 0 1 j j-1-1-j j 1 1 1 -1 -j j 1 1 J -j -1 -1 The complex multiplication with a pair of two-select-one multiplexers MUXs is easily implemented by using the following expression: R t (Re+ j Im) (-j) =Im-j Re when bi7tarybit = O Re'+ j Im'= t (Re+j Im) j=-Im+j Re when binarybit =1 The implementation architecture is shown in Fig. 3. The real part and the imaginary part are selected from the complex inputs according to the expressions above. After that, the selected

results are registered. The other three MUXs are designed in the same way. So all the complex multiplications could be realized by MUXs.

The data output from the MUXs are accumulated together which is realized in a cascade form. The results of each stage are registered. Because there are totally 64 elements to be summed up, after six cascades'addition the final result can be obtained.

Finally, the energy of the complex sum is calculated. If the energy exceeds the threshold, the chip counter and SYNC-DL code number counter are held up. As predicted, the final result has altogether 8 clock's delay, including the delay of MUXs and energy calculating.

As for the timing design of the synchronizer, all the modules except the shift register work at the main clock (81.92 MHz). Every module latches its result. Actually, it works like a pipeline. After the shift register is full, although the first result has 8 clock's delay, the matched filter outputs different results at each clock. In such a way, the matched filter can scan all the phases of all the possible SYNC-DL sequences in only one subframe (5 ms).

To implement such a coefficient reloadable matched filter, the resource expenses are estimated in Tab. 2.

Table 2. Implementation Resources Shift Register 6 * 2 * 128 = 1536 bits ROM 32 * 64 = 2048 bits Two-select-one MUX 2 * 64 = 128 blocks Inverter 2 * 64/2 = 64 blocks Adder 2 * (64+32+16+8+4+2+1) = 254 blocks Register 2 * (64+127+1) = 384 blocks Square 2 The length of the adders should be traded off between the precision and physical resources. If the accuracy is required as much as possible, the length of the adders should be assigned one bit longer along each stage, e. g. the length at the first stage is 6 and the length at the last stage should be 12. On the other hand, if the physical resources are limited, the length at every stage may be assigned to the same as 6, e. g. the tail bits are truncated. Of course, the accuracy will lose a little bit on each stage.

Because the matched filter works in a pipeline mode, every stage's result should be registered. The length of the adders mainly determines the number of registers to

be used. Besides those registers after adders, some other registers should be placed after the MUXs and the energy calculator, the number of which is also determined by the operating word length. The total registers needed are calculated with blocks in Table 2. It must be pointed out that the searching time and the working frequency should also been traded off. Of course the matched filter can work at a lower frequency. In that condition, fewer SYNC-DL sequences are read out from the ROM during 1/a chip. The result is that the matched filtering process is deployed in the time domain, but the structure of it is not to be changed.

Although the invention is described above with reference to an example shown in the attached drawings, it is apparent that the invention is not restricted to it, but can vary in many ways within the scope disclosed in the attached claims.