INPUT CIRCUIT FOR ARTIFICIAL NEURAL NETWORK ARRAY PRIORITY CLAIMS [0001] This application claims priority to U.S. Patent Application No.18/077,686, filed on December 8, 2022, and titled “Input Circuit for Artificial Neural Network Array,” and U.S. Provisional Application No.63/409,140, filed on September 22, 2022, and titled “Input Circuit and Output Circuit for Concurrent and Pipelined Operations in Artificial Neural Network Array.” FIELD OF THE INVENTION [0002] Numerous examples are disclosed of input circuitry and associated methods to implement concurrent and pipelined operations in an artificial neural network. BACKGROUND OF THE INVENTION [0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, in particular the brain) and are used to estimate or approximate functions that can depend on a large number of inputs and are generally unknown. Artificial neural networks generally include layers of interconnected "neurons" which exchange messages between each other. [0004] Figure 1 illustrates an artificial neural network, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows and have numeric weights that can be tuned based on experience. This makes neural networks adaptive to inputs and capable of learning. Typically, neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. The neurons at each level individually or collectively make a decision based on the received data from the synapses. [0005] One of the major challenges in the development of artificial neural networks for high- performance information processing is a lack of adequate hardware technology. Indeed, practical neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e., a very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or specialized graphics processing unit clusters. However, in addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low-precision analog computation. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses. [0006] Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in U.S. Patent Application Publication 2017/0337466A1, which is incorporated by reference. The non-volatile memory arrays operate as an analog neural memory and comprise non-volatile memory cells arranged in rows and columns. The neural network includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs. Non-Volatile Memory Cells [0007] Non-volatile memories are well known. For example, U.S. Patent 5,029,130 (“the ’130 patent”), which is incorporated herein by reference, discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell 210 is shown in Figure 2. Each memory cell 210 includes source region 14 and drain region 16 formed in semiconductor substrate 12, with channel region 18 there between. Floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and over a portion of the source region 14. Word line terminal 22 (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion that extends up and over the floating gate 20. The floating gate 20 and word line terminal 22 are insulated from the substrate 12 by a gate oxide. Bitline 24 is coupled to drain region 16. [0008] Memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the word line terminal 22, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation from the floating gate 20 to the word line terminal 22 via Fowler-Nordheim (FN) tunneling. [0009] Memory cell 210 is programmed by source side injection (SSI) with hot electrons (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal 22, and a positive voltage on the source region 14. Electron current will flow from the drain region 16 towards the source region 14. The electrons will accelerate and become heated when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons will be injected through the gate oxide onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20. [0010] Memory cell 210 is read by placing positive read voltages on the drain region 16 and word line terminal 22 (which turns on the portion of the channel region 18 under the word line terminal). If the floating gate 20 is positively charged (i.e., erased of electrons), then the portion of the channel region 18 under the floating gate 20 is turned on as well, and current will flow across the channel region 18, which is sensed as the erased or “1” state. If the floating gate 20 is negatively charged (i.e., programmed with electrons), then the portion of the channel region under the floating gate 20 is mostly or entirely turned off, and current will not flow (or there will be little flow) across the channel region 18, which is sensed as the programmed or “0” state. [0011] Table No.1 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 210 for performing read, erase, and program operations: Table No.1: Operation of Flash Memory Cell 210 of Figure 2 WL BL SL Program 1-2V 10.5- 9-10V [0012] Other split gate memory cell configurations, which are other types of flash memory cells, are known. For example, Figure 3 depicts a four-gate memory cell 310 comprising source region 14, drain region 16, floating gate 20 over a first portion of channel region 18, a select gate 22 (typically coupled to a word line, WL) over a second portion of the channel region 18, a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14. This configuration is described in U.S. Patent 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates are non-floating gates except floating gate 20, meaning that they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons from the channel region 18 injecting themselves onto the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30. [0013] Table No.2 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 310 for performing read, erase, and program operations: Table No.2: Operation of Flash Memory Cell 310 of Figure 3 WL/SG BL ^CG EG SL [0014] Figure 4 depicts a three-gate memory cell 410, which is another type of flash memory cell. Memory cell 410 is identical to the memory cell 310 of Figure 3 except that memory cell 410 does not have a separate control gate. The erase operation (whereby erasing occurs through use of the erase gate) and read operation are similar to that of the Figure 3 except there is no control gate bias applied. The programming operation also is done without the control gate bias, and as a result, a higher voltage is applied on the source line during a program operation to compensate for a lack of control gate bias. [0015] Table No.3 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 410 for performing read, erase, and program operations: Table No.3: Operation of Flash Memory Cell 410 of Figure 4 WL/SG BL EG SL [0016] Figure 5 depicts stacked gate memory cell 510, which is another type of flash memory cell. Memory cell 510 is similar to memory cell 210 of Figure 2, except that floating gate 20 extends over the entire channel region 18, and control gate 22 (which here will be coupled to a word line) extends over floating gate 20, separated by an insulating layer (not shown). The erase is done by FN tunneling of electrons from FG to substrate, programming is by channel hot electron (CHE) injection at region between the channel 18 and the drain region 16, by the electrons flowing from the source region 14 towards to drain region 16 and read operation which is similar to that for memory cell 210 with a higher control gate voltage. [0017] Table No.4 depicts typical voltage ranges that can be applied to the terminals of memory cell 510 and substrate 12 for performing read, erase, and program operations: Table No.4: Operation of Flash Memory Cell 510 of Figure 5 C _{G BL SL} ^Substrate Program 8-12V 3-5V 0V 0V [0018] The methods and means described herein may apply to other non-volatile memory technologies such as FINFET split gate flash or stack gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide- silicon, metal charge trap in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), CT (charge trap) memory, CN (carbon- tube) memory, OTP (bi-level or multi-level one time programmable), and CeRAM (correlated electron ram), without limitation. [0019] In order to utilize the memory arrays comprising one of the types of non-volatile memory cells described above in an artificial neural network, two modifications are made. First, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array, as further explained below. Second, continuous (analog) programming of the memory cells is provided. [0020] Specifically, the memory state (i.e., charge on the floating gate) of each memory cell in the array can be continuously changed from a fully erased state to a fully programmed state, and vice-versa, independently and with minimal disturbance of other memory cells. This means the cell storage is effectively analog or at the very least can store one of many discrete values (such as 16 or 64 different values), which allows for very precise and individual tuning of all the memory cells in the memory array, and which makes the memory array ideal for storing and making fine tuning adjustments to the synapsis weights of the neural network. Neural Networks Employing Non-Volatile Memory Cell Arrays [0021] Figure 6 conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array of the present examples. This example uses the non-volatile memory array neural network for a facial recognition application, but any other appropriate application could be implemented using a non-volatile memory array based neural network. [0022] S0 is the input layer, which for this example is a 32x32 pixel RGB image with 5 bit precision (i.e. three 32x32 pixel arrays, one for each color R, G and B, each pixel being 5 bit precision). The synapses CB1 going from input layer S0 to layer C1 apply different sets of weights in some instances and shared weights in other instances and scan the input image with 3x3 pixel overlapping filters (kernel), shifting the filter by 1 pixel (or more than 1 pixel as dictated by the model). Specifically, values for 9 pixels in a 3x3 portion of the image (i.e., referred to as a filter or kernel) are provided to the synapses CB1, where these 9 input values are multiplied by the appropriate weights and, after summing the outputs of that multiplication, a single output value is determined and provided by a first synapse of CB1 for generating a pixel of one of the feature maps of layer C1. The 3x3 filter is then shifted one pixel to the right within input layer S0 (i.e., adding the column of three pixels on the right, and dropping the column of three pixels on the left), whereby the 9 pixel values in this newly positioned filter are provided to the synapses CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process is continued until the 3x3 filter scans across the entire 32x32 pixel image of input layer S0, for all three colors and for all bits (precision values). The process is then repeated using different sets of weights to generate a different feature map of layer C1, until all the features maps of layer C1 have been calculated. [0023] In layer C1, in the present example, there are 16 feature maps, with 30x30 pixels each. Each pixel is a new feature pixel extracted from multiplying the inputs and kernel, and therefore each feature map is a two dimensional array, and thus in this example layer C1 constitutes 16 layers of two dimensional arrays (keeping in mind that the layers and arrays referenced herein are logical relationships, not necessarily physical relationships – i.e., the arrays are not necessarily oriented in physical two dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of sixteen different sets of synapse weights applied to the filter scans. The C1 feature maps could all be directed to different aspects of the same image feature, such as boundary identification. For example, the first map (generated using a first weight set, shared for all scans used to generate this first map) could identify circular edges, the second map (generated using a second weight set different from the first weight set) could identify rectangular edges, or the aspect ratio of certain features, and so on. [0024] An activation function P1 (pooling) is applied before going from layer C1 to layer S1, which pools values from consecutive, non-overlapping 2x2 regions in each feature map. The purpose of the pooling function P1 is to average out the nearby location (or a max function can also be used), to reduce the dependence of the edge location for example and to reduce the data size before going to the next stage. At layer S1, there are 1615x15 feature maps (i.e., sixteen different arrays of 15x15 pixels each). The synapses CB2 going from layer S1 to layer C2 scan maps in layer S1 with 4x4 filters, with a filter shift of 1 pixel. At layer C2, there are 2212x12 feature maps. An activation function P2 (pooling) is applied before going from layer C2 to layer S2, which pools values from consecutive non-overlapping 2x2 regions in each feature map. At layer S2, there are 226x6 feature maps. An activation function (pooling) is applied at the synapses CB3 going from layer S2 to layer C3, where every neuron in layer C3 connects to every map in layer S2 via a respective synapse of CB3. At layer C3, there are 64 neurons. The synapses CB4 going from layer C3 to the output layer S3 fully connects C3 to S3, i.e. every neuron in layer C3 is connected to every neuron in layer S3. The output at S3 includes 10 neurons, where the highest output neuron determines the class. This output could, for example, be indicative of an identification or classification of the contents of the original image. [0025] Each layer of synapses is implemented using an array, or a portion of an array, of non- volatile memory cells. [0026] Figure 7 is a block diagram of an array that can be used for that purpose. Vector-by- matrix multiplication (VMM) array 32 includes non-volatile memory cells and is utilized as the synapses (such as CB1, CB2, CB3, and CB4 in Figure 6) between one layer and the next layer. Specifically, VMM array 32 includes an array of non-volatile memory cells 33, erase gate and word line gate decoder 34, control gate decoder 35, bit line decoder 36 and source line decoder 37, which decode the respective inputs for the non-volatile memory cell array 33. Input to VMM array 32 can be from the erase gate and wordline gate decoder 34 or from the control gate decoder 35. Source line decoder 37 in this example also decodes the output of the non-volatile memory cell array 33. Alternatively, bit line decoder 36 can decode the output of the non- volatile memory cell array 33. [0027] Non-volatile memory cell array 33 serves two purposes. First, it stores the weights that will be used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33 and adds them up per output line (source line or bit line) to produce the output, which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, the non-volatile memory cell array 33 negates the need for separate multiplication and addition logic circuits and is also power efficient due to its in-situ memory computation. [0028] The output of non-volatile memory cell array 33 is supplied to a differential summer (such as a summing op-amp or a summing current mirror) 38, which sums up the outputs of the non-volatile memory cell array 33 to create a single value for that convolution. The differential summer 38 is arranged to perform summation of positive weight and negative weight. [0029] The summed-up output values of differential summer 38 are then supplied to an activation function block 39, which rectifies the output. The activation function block 39 may provide sigmoid, tanh, or ReLU functions. The rectified output values of activation function block 39 become an element of a feature map as the next layer (e.g. C1 in Figure 6), and are then applied to the next synapse to produce the next feature map layer or final layer. Therefore, in this example, non-volatile memory cell array 33 constitutes a plurality of synapses (which receive their inputs from the prior layer of neurons or from an input layer such as an image database), and summing op-amp 38 and activation function block 39 constitute a plurality of neurons. [0030] The input to VMM array 32 in Figure 7 (WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, or digital bits (in which case a DAC is provided to convert digital bits to appropriate input analog level) and the output can be analog level, binary level, or digital bits (in which case an output ADC is provided to convert output analog level into digital bits). [0031] Figure 8 is a block diagram depicting the usage of numerous layers of VMM arrays 32, here labeled as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in Figure 8, the input, denoted Inputx, is converted from digital to analog by a digital-to-analog converter 31 and provided to input VMM array 32a. The converted analog inputs could be voltage or current. The input D/A conversion for the first layer could be done by using a function or a LUT (look up table) that maps the inputs Inputx to appropriate analog levels for the matrix multiplier of input VMM array 32a. The input conversion could also be done by an analog to analog (A/A) converter to convert an external analog input to a mapped analog input to the input VMM array 32a. [0032] The output generated by input VMM array 32a is provided as an input to the next VMM array (hidden level 1) 32b, which in turn generates an output that is provided as an input to the next VMM array (hidden level 2) 32c, and so on. The various layers of VMM array 32 function as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a stand-alone, physical non-volatile memory array, or multiple VMM arrays could utilize different portions of the same physical non-volatile memory array, or multiple VMM arrays could utilize overlapping portions of the same physical non-volatile memory array. The example shown in Figure 8 contains five layers (32a,32b,32c,32d,32e): one input layer (32a), two hidden layers (32b,32c), and two fully connected layers (32d,32e). One of ordinary skill in the art will appreciate that this is merely an example and that a system instead could comprise more than two hidden layers and more than two fully connected layers. Vector-by-Matrix Multiplication (VMM) Arrays [0033] Figure 9 depicts neuron VMM array 900, which is particularly suited for memory cells 310 as shown in Figure 3 and is utilized as the synapses and parts of neurons between an input layer and the next layer. VMM array 900 comprises memory array 901 of non-volatile memory cells and reference array 902 (at the top of the array) of non-volatile reference memory cells. Alternatively, another reference array can be placed at the bottom. [0034] In VMM array 900, control gate lines, such as control gate line 903, run in a vertical direction (hence reference array 902 in the row direction is orthogonal to control gate line 903), and erase gate lines, such as erase gate line 904, run in a horizontal direction. Here, the inputs to VMM array 900 are provided on the control gate lines (CG0, CG1, CG2, CG3), and the output of VMM array 900 emerges on the source lines (SL0, SL1). In one example, only even rows are used, and in another example, only odd rows are used. The current placed on each source line (SL0, SL1, respectively) performs a summing function of all the currents from the memory cells connected to that particular source line. [0035] As described herein for neural networks, the non-volatile memory cells of VMM array 900, i.e., the memory cells 310 of VMM array 900, may be configured to operate in a sub- threshold region. [0036] The non-volatile reference memory cells and the non-volatile memory cells described herein are biased in weak inversion (sub threshold region): Ids = Io * e ^{(Vg- Vth)/nVt} = w * Io * e ^(Vg)/nVt , where Ids is the drain to h is threshold voltage of the memory cell; Vt is thermal voltage = k*T/q with k being the Boltzmann constant, T the temperature in Kelvin, and q the electronic charge; n is a slope factor = 1 + (Cdep/Cox) with Cdep = capacitance of the depletion layer, and Cox capacitance of the gate oxide layer; Io is the memory cell current at gate voltage equal to threshold voltage, Io is proportional to (Wt/L)*u*Cox* (n-1) * Vt ² where u is carrier mobility and Wt and L are width and length, respectively, of the memory cell. [0037] For an I-to-V log converter using a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert input current into an input voltage: Vg= n*Vt*log [Ids/wp*Io] where, wp is w of a reference o [0038] For a memory array use d as a vector matrix multiplier VMM array with the current input, the output current is: Iout = wa * Io * e ^(Vg)/nVt namely Here, wa = w of each mem Vthp is effective threshold voltage of the peripheral memory cell and Vtha is effective threshold voltage of the main (data) memory cell. Note that the threshold voltage of a transistor is a function of substrate body bias voltage and the substrate body bias voltage, denoted Vsb, can be modulated to compensate for various conditions, on such temperature. The threshold voltage Vth can be expressed as: Vth = Vth0 + gamma (SQRT |Vsb – 2*ϕF) - SQRT |2* ϕF |) where Vth0 is threshold voltage with zero substrate bias, ϕF is a surface potential, and gamma is a body effect parameter. [0039] A wordline or control gate can be used as the input for the memory cell for the input voltage. [0040] Alternatively, the flash memory cells of VMM arrays described herein can be configured to operate in the linear region: Ids = beta* (Vgs-Vth)*Vds ; beta = u*Cox*Wt/L W = α (Vgs-Vth) meaning weight W in the linear region is proportional to (Vgs-Vth) [0041] A wordline or control gate or bitline or sourceline can be used as the input for the memory cell operated in the linear region. The bitline or sourceline can be used as the output for the memory cell. [0042] For an I-to-V linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor operating in the linear region can be used to linearly convert an input/output current into an input/output voltage. [0043] Alternatively, the memory cells of VMM arrays described herein can be configured to operate in the saturation region: Ids = ½ * beta* (Vgs-Vth) ² ; beta = u*Cox*Wt/L Wα (Vgs-Vth) ² , meaning weight W is proportional to (Vgs-Vth) ² [0044] A wordline, control gate, or erase gate can be used as the input for the memory cell operated in the saturation region. The bitline or sourceline can be used as the output for the output neuron. [0045] Alternatively, the memory cells of VMM arrays described herein can be used in all regions or a combination thereof (sub threshold, linear, or saturation) for each layer or multi layers of a neural network. [0046] Other examples for VMM array 32 of Figure 7 are described in U.S. Patent No. 10,748,630, which is incorporated by reference herein. As described in that application. a sourceline or a bitline can be used as the neuron output (current summation output). [0047] Figure 10 depicts neuron VMM array 1000, which is particularly suited for memory cells 210 as shown in Figure 2 and is utilized as the synapses between an input layer and the next layer. VMM array 1000 comprises a memory array 1003 of non-volatile memory cells, reference array 1001 of first non-volatile reference memory cells, and reference array 1002 of second non- volatile reference memory cells. Reference arrays 1001 and 1002, arranged in the column direction of the array, serve to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In effect, the first and second non-volatile reference memory cells are diode-connected through multiplexors 1014 (only partially depicted) with current inputs flowing into them. The reference cells are tuned (e.g., programmed) to target reference levels. The target reference levels are provided by a reference mini-array matrix (not shown). [0048] Memory array 1003 serves two purposes. First, it stores the weights that will be used by the VMM array 1000 on respective memory cells thereof. Second, memory array 1003 effectively multiplies the inputs (i.e. current inputs provided in terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1001 and 1002 convert into the input voltages to supply to wordlines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1003 and then adds all the results (memory cell currents) to produce the output on the respective bit lines (BL0 - BLN), which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, memory array 1003 negates the need for separate multiplication and addition logic circuits and is also power efficient. Here, the voltage inputs are provided on the word lines WL0, WL1, WL2, and WL3, and the output emerges on the respective bit lines BL0 - BLN during a read (inference) operation. The current placed on each of the bit lines BL0 - BLN performs a summing function of the currents from all non-volatile memory cells connected to that particular bitline. [0049] Table No.5 depicts operating voltages and currents for VMM array 1000. The columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, source lines for selected cells, and source lines for unselected cells. The rows indicate the operations of read, erase, and program. WEST\301059868.1 Table No.5: Operation of VMM Array 1000 of Figure 10: 210 as shown in Figure 2 and is utilized as the synapses and parts of neurons between an input layer and the next layer. VMM array 1100 comprises a memory array 1103 of non-volatile memory cells, reference array 1101 of first non-volatile reference memory cells, and reference array 1102 of second non-volatile reference memory cells. Reference arrays 1101 and 1102 run in row direction of the VMM array 1100. VMM array is similar to VMM 1000 except that in VMM array 1100, the word lines run in the vertical direction. Here, the inputs are provided on the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and the output emerges on the source line (SL0, SL1) during a read operation. The current placed on each source line performs a summing function of all the currents from the memory cells connected to that particular source line. [0051] Table No.6 depicts operating voltages and currents for VMM array 1100. The columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, source lines for selected cells, and source lines for unselected cells. The rows indicate the operations of read, erase, and program. Table No.6: Operation of VMM Array 1100 of Figure 11 - 310 as shown in Figure 3 and is utilized as the synapses and parts of neurons between an input layer and the next layer. VMM array 1200 comprises a memory array 1203 of non-volatile memory cells, reference array 1201 of first non-volatile reference memory cells, and reference array 1202 of second non-volatile reference memory cells. Reference arrays 1201 and 1202 serve to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In effect, the first and second non-volatile reference memory cells are diode-connected through multiplexors 1212 (only partially shown) with current inputs flowing into them through BLR0, BLR1, BLR2, and BLR3. Multiplexors 1212 each include a respective multiplexor 1205 and a cascoding transistor 1204 to ensure a constant voltage on the bitline (such as BLR0) of each of the first and second non-volatile reference memory cells during a read operation. The reference cells are tuned to target reference levels. [0053] Memory array 1203 serves two purposes. First, it stores the weights that will be used by the VMM array 1200. Second, memory array 1203 effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, for which reference arrays 1201 and 1202 convert these current inputs into the input voltages to supply to the control gates (CG0, CG1, CG2, and CG3) by the weights stored in the memory array and then add all the results (cell currents) to produce the output, which appears on BL0 – BLN, and will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, the memory array negates the need for separate multiplication and addition logic circuits and is also power efficient. Here, the inputs are provided on the control gate lines (CG0, CG1, CG2, and CG3), and the output emerges on the bit lines (BL0 – BLN) during a read operation. The current placed on each bitline performs a summing function of all the currents from the memory cells connected to that particular bitline. [0054] VMM array 1200 implements uni-directional tuning for non-volatile memory cells in memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is placed on the floating gate (such that the wrong value is stored in the cell), the cell is erased and the sequence of partial programming operations starts over. As shown, two rows sharing the same erase gate (such as EG0 or EG1) are erased together (which is known as a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached. [0055] Table No.7 depicts operating voltages and currents for VMM array 1200. The columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, control gates for selected cells, control gates for unselected cells in the same sector as the selected cells, control gates for unselected cells in a different sector than the selected cells, erase gates for selected cells, erase gates for unselected cells, source lines for selected cells, and source lines for unselected cells. The rows indicate the operations of read, erase, and program. Table No.7: Operation of VMM Array 1200 of Figure 12 CG - Erase 0V 0V 0V 0V 0V 0-2.6V 0-2.6V 5-12V 0-2.6V 0V 0V 310 as shown in Figure 3, and is utilized as the synapses and parts of neurons between an input layer and the next layer. VMM array 1300 comprises a memory array 1303 of non-volatile memory cells, reference array 1301 or first non-volatile reference memory cells, and reference array 1302 of second non-volatile reference memory cells. EG lines EGR0, EG0, EG1 and EGR1 are run vertically while CG lines CG0, CG1, CG2 and CG3 and SL lines WL0, WL1, WL2 and WL3 are run horizontally. VMM array 1300 is similar to VMM array 1400, except that VMM array 1300 implements bi-directional tuning, where each individual cell can be completely erased, partially programmed, and partially erased as needed to reach the desired amount of charge on the floating gate due to the use of separate EG lines. As shown, reference arrays 1301 and 1302 convert input current in the terminal BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells through multiplexors 1314) to be applied to the memory cells in the row direction. The current output (neuron) is in the bit lines BL0 – BLN, where each bit line sums all currents from the non- volatile memory cells connected to that particular bitline. [0057] Table No.8 depicts operating voltages and currents for VMM array 1300. The columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, control gates for selected cells, control gates for unselected cells in the same sector as the selected cells, control gates for unselected cells in a different sector than the selected cells, erase gates for selected cells, erase gates for unselected cells, source lines for selected cells, and source lines for unselected cells. The rows indicate the operations of read, erase, and program. Table No.8: Operation of VMM Array 1300 of Figure 13 CG -unsel 210 as shown in Figure 2 and is utilized as the synapses and parts of neurons between an input layer and the next layer. In VMM array 2200, the inputs INPUT ₀ . …, INPUT _N are received on bit lines BL ₀ , ... BL _N , respectively, and the outputs OUTPUT ₁ , OUTPUT ₂ , OUTPUT ₃ , and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively. [0059] Figure 23 depicts neuron VMM array 2300, which is particularly suited for memory cells 210 as shown in Figure 2 and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and the outputs OUTPUT0, ... OUTPUT _N are generated on bit lines BL ₀ , …, BL _N . [0060] Figure 24 depicts neuron VMM array 2400, which is particularly suited for memory cells 210 as shown in Figure 2, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT _0, …, INPUT _M are received on word lines WL ₀ , …, WL _M , respectively, and the outputs OUTPUT ₀ , ... OUTPUT _N are generated on bit lines BL0, …, BLN. [0061] Figure 25 depicts neuron VMM array 2500, which is particularly suited for memory cells 310 as shown in Figure 3, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT0, …, INPUTM are received on word lines WL ₀ , …, WL _M , respectively, and the outputs OUTPUT ₀ , ... OUTPUT _N are generated on bit lines BL0, …, BLN. [0062] Figure 26 depicts neuron VMM array 2600, which is particularly suited for memory cells 410 as shown in Figure 4, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT0, …, INPUTn are received on vertical control gate lines CG0, …, CGN, respectively, and the outputs OUTPUT1 and OUTPUT2 are generated on source lines SL ₀ and SL ₁ . [0063] Figure 27 depicts neuron VMM array 2700, which is particularly suited for memory cells 410 as shown in Figure 4 and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT0, …, INPUTN are received on the gates of bit line control gates 2701-1, 2701-2, …, 2701-(N-1), and 2701-N, respectively, which are coupled to bit lines BL0, …, BLN, respectively. Example outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1. [0064] Figure 28 depicts neuron VMM array 2800, which is particularly suited for memory cells 310 as shown in Figure 3, memory cells 510 as shown in Figure 5, and memory cells 710 as shown in Figure 7, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT _0, …, INPUT _M are received on word lines WL ₀ , …, WL _M , and the outputs OUTPUT _0, …, OUTPUT _N are generated on bit lines BL ₀ , …, BLN, respectively. [0065] Figure 29 depicts neuron VMM array 2900, which is particularly suited for memory cells 310 as shown in Figure 3, memory cells 510 as shown in Figure 5, and memory cells 710 as shown in Figure 7, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT0, …, INPUTM are received on control gate lines CG ₀ , …, CG _M . Outputs OUTPUT _0, …, OUTPUT _N are generated on vertical source lines SL0, …, SLN, respectively, where each source line SLi is coupled to the source lines of all memory cells in column i. [0066] Figure 30 depicts neuron VMM array 3000, which is particularly suited for memory cells 310 as shown in Figure 3, memory cells 510 as shown in Figure 5, and memory cells 710 as shown in Figure 7, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT0, …, INPUTM are received on control gate lines CG ₀ , …, CG _M . Outputs OUTPUT _0, …, OUTPUT _N are generated on vertical bit lines BL ₀ , …, BLN, respectively, where each bit line BLi is coupled to the bit lines of all memory cells in column i. Long Short-Term Memory [0067] The prior art includes a concept known as long short-term memory (LSTM). LSTM units often are used in neural networks. LSTM allows a neural network to remember information over predetermined arbitrary time intervals and to use that information in subsequent operations. A conventional LSTM unit comprises a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the time interval that the information is remembered in the LSTM. VMMs are particularly useful in LSTM units. [0068] Figure 14 depicts an example LSTM 1400. LSTM 1400 in this example comprises cells 1401, 1402, 1403, and 1404. Cell 1401 receives input vector x0 and generates output vector h0 and cell state vector c ₀ . Cell 1402 receives input vector x ₁ , the output vector (hidden state) h ₀ from cell 1401, and cell state c0 from cell 1401 and generates output vector h1 and cell state vector c1. Cell 1403 receives input vector x2, the output vector (hidden state) h1 from cell 1402, and cell state c ₁ from cell 1402 and generates output vector h ₂ and cell state vector c ₂ . Cell 1404 receives input vector x ₃ , the output vector (hidden state) h ₂ from cell 1403, and cell state c ₂ from cell 1403 and generates output vector h3. Additional cells can be used, and an LSTM with four cells is merely an example. [0069] Figure 15 depicts an example implementation of an LSTM cell 1500, which can be used for cells 1401, 1402, 1403, and 1404 in Figure 14. LSTM cell 1500 receives input vector x(t), cell state vector c(t-1) from a preceding cell, and output vector h(t-1) from a preceding cell, and generates cell state vector c(t) and output vector h(t). [0070] LSTM cell 1500 comprises sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control how much of each component in the input vector is allowed through to the output vector. LSTM cell 1500 also comprises tanh devices 1504 and 1505 to apply a hyperbolic tangent function to an input vector, multiplier devices 1506, 1507, and 1508 to multiply two vectors together, and addition device 1509 to add two vectors together. Output vector h(t) can be provided to the next LSTM cell in the system, or it can be accessed for other purposes. [0071] Figure 16 depicts an LSTM cell 1600, which is an example of an implementation of LSTM cell 1500. For the reader’s convenience, the same numbering from LSTM cell 1500 is used in LSTM cell 1600. Sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 each comprise multiple VMM arrays 1601 and activation function blocks 1602. Thus, it can be seen that VMM arrays are particular useful in LSTM cells used in certain neural network systems. The multiplier devices 1506, 1507, and 1508 and the addition device 1509 are implemented in a digital manner or in an analog manner. The activation function blocks 1602 can be implemented in a digital manner or in an analog manner. [0072] An alternative to LSTM cell 1600 (and another example of an implementation of LSTM cell 1500) is shown in Figure 17. In Figure 17, sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 share the same physical hardware (VMM arrays 1701 and activation function block 1702) in a time-multiplexed fashion. LSTM cell 1700 also comprises multiplier device 1703 to multiply two vectors together, addition device 1708 to add two vectors together, tanh device 1505 (which comprises activation function block 1702), register 1707 to store the value i(t) when i(t) is output from sigmoid function block 1702, register 1704 to store the value f(t) * c(t-1) when that value is output from multiplier device 1703 through multiplexor 1710, register 1705 to store the value i(t) * u(t) when that value is output from multiplier device 1703 through multiplexor 1710, and register 1706 to store the value o(t) * c~(t) when that value is output from multiplier device 1703 through multiplexor 1710, and multiplexor 1709. [0073] Whereas LSTM cell 1600 contains multiple sets of VMM arrays 1601 and respective activation function blocks 1602, LSTM cell 1700 contains only one set of VMM arrays 1701 and activation function block 1702, which are used to represent multiple layers in the example of LSTM cell 1700. LSTM cell 1700 will require less space than LSTM 1600, as LSTM cell 1700 will require 1/4 as much space for VMMs and activation function blocks compared to LSTM cell 1600. [0074] It can be further appreciated that LSTM units will typically comprise multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation function block and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. The examples described below therefore reduce the circuitry required outside of the VMM arrays themselves. Gated Recurrent Units [0075] An analog VMM implementation can be utilized for a GRU (gated recurrent unit) system. GRUs are a gating mechanism in recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than an LSTM cell. [0076] Figure 18 depicts an example GRU 1800. GRU 1800 in this example comprises cells 1801, 1802, 1803, and 1804. Cell 1801 receives input vector x ₀ and generates output vector h ₀ . Cell 1802 receives input vector x1, the output vector h0 from cell 1801 and generates output vector h1. Cell 1803 receives input vector x2 and the output vector (hidden state) h1 from cell 1802 and generates output vector h ₂ . Cell 1804 receives input vector x ₃ and the output vector (hidden state) h2 from cell 1803 and generates output vector h3. Additional cells can be used, and an GRU with four cells is merely an example. [0077] Figure 19 depicts an example implementation of a GRU cell 1900, which can be used for cells 1801, 1802, 1803, and 1804 of Figure 18. GRU cell 1900 receives input vector x(t) and output vector h(t-1) from a preceding GRU cell and generates output vector h(t). GRU cell 1900 comprises sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to components from output vector h(t-1) and input vector x(t). GRU cell 1900 also comprises a tanh device 1903 to apply a hyperbolic tangent function to an input vector, a plurality of multiplier devices 1904, 1905, and 1906 to multiply two vectors together, an addition device 1907 to add two vectors together, and a complementary device 1908 to subtract an input from 1 to generate an output. [0078] Figure 20 depicts a GRU cell 2000, which is an example of an implementation of GRU cell 1900. For the reader’s convenience, the same numbering from GRU cell 1900 is used in GRU cell 2000. As can be seen in Figure 20, sigmoid function devices 1901 and 1902, and tanh device 1903 each comprise multiple VMM arrays 2001 and activation function blocks 2002. Thus, it can be seen that VMM arrays are of particular use in GRU cells used in certain neural network systems. The multiplier devices 1904, 1905, 1906, the addition device 1907, and the complementary device 1908 are implemented in a digital manner or in an analog manner. The activation function blocks 2002 can be implemented in a digital manner or in an analog manner. [0079] An alternative to GRU cell 2000 (and another example of an implementation of GRU cell 1900) is shown in Figure 21. In Figure 21, GRU cell 2100 utilizes VMM arrays 2101 and activation function block 2102, which when configured as a sigmoid function applies a number between 0 and 1 to control how much of each component in the input vector is allowed through to the output vector. In Figure 21, sigmoid function devices 1901 and 1902 and tanh device 1903 share the same physical hardware (VMM arrays 2101 and activation function block 2102) in a time-multiplexed fashion. GRU cell 2100 also comprises multiplier device 2103 to multiply two vectors together, addition device 2105 to add two vectors together, complementary device 2109 to subtract an input from 1 to generate an output, multiplexor 2104, register 2106 to hold the value h(t-1) * r(t) when that value is output from multiplier device 2103 through multiplexor 2104, register 2107 to hold the value h(t-1) *z(t) when that value is output from multiplier device 2103 through multiplexor 2104, and register 2108 to hold the value h^(t) * (1-z(t)) when that value is output from multiplier device 2103 through multiplexor 2104. [0080] Whereas GRU cell 2000 contains multiple sets of VMM arrays 2001 and activation function blocks 2002, GRU cell 2100 contains only one set of VMM arrays 2101 and activation function block 2102, which are used to represent multiple layers in the example of GRU cell 2100. GRU cell 2100 will require less space than GRU cell 2000, as GRU cell 2100 will require 1/3 as much space for VMMs and activation function blocks compared to GRU cell 2000. [0081] It can be further appreciated that GRU systems will typically comprise multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation function block and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. The examples described below therefore reduce the circuitry required outside of the VMM arrays themselves. [0082] The input to the VMM arrays can be an analog level, a binary level, a pulse, a time modulated pulse, or digital bits (in this case a DAC is needed to convert digital bits to appropriate input analog level) and the output can be an analog level, a binary level, a timing pulse, pulses, or digital bits (in this case an output ADC is needed to convert output analog level into digital bits). [0083] In general, for each memory cell in a VMM array, each weight W can be implemented by a single memory cell or by a differential cell or by two blend memory cells (average of 2 cells). In the differential cell case, two memory cells are needed to implement a weight W as a differential weight (W = W+ – W-). In the two blend memory cells, two memory cells are needed to implement a weight W as an average of two cells. [0084] Figure 31 depicts VMM system 3100. In some examples, the weights, W, stored in a VMM array are stored as differential pairs, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). In VMM system 3100, half of the bit lines are designated as W+ lines, that is, bit lines connecting to memory cells that will store positive weights W+, and the other half of the bit lines are designated as W- lines, that is, bit lines connecting to memory cells implementing negative weights W-. The W- lines are interspersed among the W+ lines in an alternating fashion. The subtraction operation is performed by a summation circuit that receives current from a W+ line and a W- line, such as summation circuits 3101 and 3102. The output of a W+ line and the output of a W- line are combined together to give effectively W = W+ - W- for each pair of (W+, W-) cells for all pairs of (W+, W-) lines. While the above has been described in relation to W- lines interspersed among the W+ lines in an alternating fashion, in other examples W+ lines and W- lines can be arbitrarily located anywhere in the array. [0085] Figure 32 depicts another example. In VMM system 3210, positive weights W+ are implemented in first array 3211 and negative weights W- are implemented in a second array 3212, second array 3212 separate from the first array, and the resulting weights are appropriately combined together by summation circuits 3213. [0086] Figure 33 depicts VMM system 3300. the weights, W, stored in a VMM array are stored as differential pairs, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). VMM system 3300 comprises array 3301 and array 3302. Half of the bit lines in each of array 3301 and 3302 are designated as W+ lines, that is, bit lines connecting to memory cells that will store positive weights W+, and the other half of the bit lines in each of array 3301 and 3302 are designated as W- lines, that is, bit lines connecting to memory cells implementing negative weights W-. The W- lines are interspersed among the W+ lines in an alternating fashion. The subtraction operation is performed by a summation circuit that receives current from a W+ line and a W- line, such as summation circuits 3303, 3304, 3305, and 3306. The output of a W+ line and the output of a W- line from each array 3301, 3302 are respectively combined together to give effectively W = W+ - W- for each pair of (W+, W-) cells for all pairs of (W+, W-) lines. In addition, the W values from each array 3301 and 3302 can be further combined through summation circuits 3307 and 3308, such that each W value is the result of a W value from array 3301 minus a W value from array 3302, meaning that the end result from summation circuits 3307 and 3308 is a differential value of two differential values. [0087] Each non-volatile memory cells used in the analog neural memory system is to be erased and programmed to hold a very specific and precise amount of charge, i.e., the number of electrons, in the floating gate. For example, each floating gate should hold one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include 16, 32, 64, 128, and 256. [0088] Prior art VMM systems require significant area and involve significant latency at the input stage and output stage. In the input stage, multiple clock cycles are required to load activation data into row registers prior to a programming operation. For example, for an 8-bit I/O, 8-bits of activation data are needed for each row, which typically number 1024 rows or more, which require a clock cycle per row, or 1024 clock cycles if there are 1024 rows, resulting in latency between 10 ns and 10 µs. In the output stage, shifting out neuron output data involves latency as well. For example, for a 128 ADC, 128 clocks are needed for an 8-bit output. [0089] It is desirable to reduce latency at the input stage and output stage to increase the overall speed of operation of the artificial neural network. SUMMARY OF THE INVENTION [0090] Numerous examples are disclosed of input circuitry and output circuitry and associated methods to implement concurrent and pipelined operations in an artificial neural network. BRIEF DESCRIPTION OF THE DRAWINGS [0091] Figure 1 is a diagram that illustrates an artificial neural network. [0092] Figure 2 depicts a prior art split gate flash memory cell. [0093] Figure 3 depicts another prior art split gate flash memory cell. [0094] Figure 4 depicts another prior art split gate flash memory cell. [0095] Figure 5 depicts another prior art split gate flash memory cell. [0096] Figure 6 is a diagram illustrating the different levels of an exemplary artificial neural network utilizing one or more non-volatile memory arrays. [0097] Figure 7 is a block diagram illustrating a VMM system. [0098] Figure 8 is a block diagram illustrates an example artificial neural network utilizing one or more VMM systems. [0099] Figure 9 depicts another example of a VMM system. [00100] Figure 10 depicts another example of a VMM system. [00101] Figure 11 depicts another example of a VMM system. [00102] Figure 12 depicts another example of a VMM system. [00103] Figure 13 depicts another example of a VMM system. [00104] Figure 14 depicts a prior art long short-term memory system. [00105] Figure 15 depicts an example cell for use in a long short-term memory system. [00106] Figure 16 depicts an example implementation of the cell of Figure 15. [00107] Figure 17 depicts another example implementation of the cell of Figure 15. [00108] Figure 18 depicts a prior art gated recurrent unit system. [00109] Figure 19 depicts an example cell for use in a gated recurrent unit system. [00110] Figure 20 depicts an example implementation t of the cell of Figure 19. [00111] Figure 21 depicts another example implementation of the cell of Figure 19. [00112] Figure 22 depicts another example of a VMM system. [00113] Figure 23 depicts another example of a VMM system. [00114] Figure 24 depicts another example of a VMM system. [00115] Figure 25 depicts another example of a VMM system. [00116] Figure 26 depicts another example of a VMM system. [00117] Figure 27 depicts another example of a VMM system. [00118] Figure 28 depicts another example of a VMM system. [00119] Figure 29 depicts another example of a VMM system. [00120] Figure 30 depicts another example of a VMM system. [00121] Figure 31 depicts another example of a VMM system. [00122] Figure 32 depicts another example of a VMM system. [00123] Figure 33 depicts another example of a VMM system. [00124] Figure 34 depicts another example of a VMM system. [00125] Figures 35A and 35B depict input blocks for a VMM system. [00126] Figure 36 depicts an input block for a VMM system. [00127] Figure 37A and 37B depict signals associated with input operations for a VMM array. [00128] Figure 38A depicts an input block for a VMM system. [00129] Figure 38B depicts an input method. [00130] Figures 39A, 39B, 39C, and 39D depict input blocks for a VMM system. [00131] Figure 40A depicts an output block for a VMM system. [00132] Figure 40B depicts an output block for a VMM system. [00133] Figure 40C depicts an output block for a VMM system. [00134] Figure 41 depicts waveforms for a VMM system. [00135] Figure 42 depicts waveforms for a VMM system. [00136] Figure 43 depicts waveforms for a VMM system. [00137] Figure 44 depicts waveforms for a VMM system. [00138] Figure 45 depicts a neural read operation method. [00139] Figure 46 depicts a neural read operation method. [00140] Figure 47 depicts a neural read operation method. [00141] Figure 48 depicts a neural read operation method. [00142] Figure 49 depicts a neural read operation method. DETAILED DESCRIPTION OF THE INVENTION VMM System Architecture [00143] Figure 34 depicts a block diagram of VMM system 3400. VMM system 3400 comprises VMM array 3401, row decoder 3402, high voltage decoder 3403, column decoders 3404, bit line drivers 3405 (such as bit line control circuitry for programming), input circuit 3406, output circuit 3407, control logic 3408, and bias generator 3409. VMM system 3400 further comprises high voltage generation block 3410, which comprises charge pump 3411, charge pump regulator 3412, and high voltage level generator 3413. VMM system 3400 further comprises (program/erase, or weight tuning) algorithm controller 3414, analog circuitry 3415, control engine 3416 (that may include special functions such as arithmetic functions, activation functions, embedded microcontroller logic, without limitation), test control logic 3417, and static random access memory (SRAM) block 3418 to store intermediate data such as for input circuits (e.g., activation data) or output circuits (neuron output data, partial sum output neuron data) or data in for programming (such as data in for a whole row or for multiple rows). [00144] The input circuit 3406 may include circuits such as a DAC (digital to analog converter), DPC (digital to pulses converter, digital to time modulated pulse converter), AAC (analog to analog converter, such as a current to voltage converter, logarithmic converter), PAC (pulse to analog level converter), or any other type of converters. The input circuit 3406 may implement one or more of normalization, linear or non-linear up/down scaling functions, or arithmetic functions. The input circuit 3406 may implement a temperature compensation function for input levels. The input circuit 3406 may implement an activation function such as ReLU or sigmoid. Input circuit 3406 may store digital activation data to be applied as, or combined with, an input signal during a program or read operation. The digital activation data can be stored in registers. Input circuit 3406 may comprise circuits to drive the array terminals, such as CG, WL, EG, and SL lines, which may include sample-and-hold circuits and buffers. A DAC can be used to convert digital activation data into an analog input voltage to be applied to the array. [00145] The output circuit 3407 may include circuits such as an ITV (current-to-voltage circuit), ADC (analog to digital converter, to convert neuron analog output to digital bits), AAC (analog to analog converter, such as a current to voltage converter, logarithmic converter), APC (analog to pulse(s) converter, analog to time modulated pulse converter), or any other type of converters. The output circuit 3407 may convert array outputs into activation data. The output circuit 3407 may implement an activation function such as rectified linear activation function (ReLU) or sigmoid. The output circuit 3407 may implement one or more of statistic normalization, regularization, up/down scaling/gain functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) for neuron outputs. The output circuit 3407 may implement a temperature compensation function for neuron outputs or array outputs (such as bitline output) so as to keep power consumption of the array approximately constant or to improve precision of the array (neuron) outputs such as by keeping the IV slope approximately the same over temperature. The output circuit 3407 may comprise registers for storing output data. [00146] Figure 35A depicts input block 3500 to be used to provide inputs to VMM array 3401. Input block 3500 comprises global digital-to-analog converter (DAC) 3501; row registers 3502-0 through 3502-n, respectively corresponding to one of the rows numbered 0 through n in the array; digital comparator blocks 3503-0 through 3503-n, respectively corresponding to one of the rows numbered 0 through n in the array; row sample-and-hold buffers 3504-0 through 3504- n, respectively corresponding to one of the rows numbered 0 through n in the array; and output signals 3505-0 through 3505-n, respectively corresponding to one of the rows numbered 0 through n in the array, and denoted CGIN0, CGIN1…, CGINn-1 and CGINn, respectively. Signal GDACsup is the global DAC signal supplied by the global DAC 3501. The signals CGIN0 to CGINn couple to the respective row inputs of the array 3401. CLKDAC is an input clock for GDAC for providing analog output values. In one example, these analog output values correspond to counts of the CLKDAC clock. [00147] Digital comparator blocks 3503 compare the value stored in the associated row register 3502 against signal CLKCOUNTx. CLKCOUNTx is a result of a counter which counter counts a clock signal during a predetermined interval; if it matches, then the corresponding row S/H 3504 is enabled by the respective digital comparator block 3503 to sample the value from the global DAC 3501 into the respective row S/H buffer. This technique will be referred to as global row DAC sampling. As indicated above, each row in VMM array 3401 has a corresponding row register 3502, digital comparator block 3503, and row S/H 3504. [00148] During operation, row registers 3502-0 through 3502-n are loaded with digital input bits DINx (where x is the number of bits, such as 8 or 16 bits) for that particular row and receives a clock signal, CLK. The CLK signal is used to load in the data from the digital input bits DINx into the respective row registers 3502-x. Global DAC 3501 is shared by all rows, and in a time-multiplexed fashion, performs a digital-to-analog conversion on the digital bits DINx stored in a particular row register 3502. The conversion is done by comparing the digital input bits of a particular row versus signal CLKCOUNTx, which is a digital counting value, by each of the digital comparator blocks 3503. When the digital counting values of the signal CLKCOUNTx matches the contents of the respective row register 3502, the corresponding row sample-and-hold buffer 3504 for that row samples the analog output from global DAC 3501 and holds that value, which is then applied as output signal 3505 for that particular row. Output signal 3504 can be applied, for example, to a control gate line or a word line or erase gate during a programming operation in that particular row, in the manner described above with respect to other Figures. [00149] Alternatively, a row sample-and-hold buffer 3504 can be shared between two or more rows by time multiplexing the row sample-and-hold buffers. [00150] Figure 35B depicts input block 3550 to be used to provide inputs to VMM array 3401. Input block 3550 comprises global digital-to-analog converter (DAC) 3551; row registers 3552-0 through 3552-n, respectively corresponding to a one of the rows numbered 0 through n in the VMM array 3401; digital multiplexer (mux) blocks 3553-0 through 3553-n, respectively corresponding to one of the rows numbered 0 through n; row sample-and-hold (S/H) buffers 3554-0 through 3554-n, respectively corresponding to one of the rows numbered 0 through n; and output signals 3555-0 through 3555-n, denoted CGIN0, CGIN1…, CGINn-1 and CGINn, respectively, respectively corresponding to one of the rows numbered 0 through n. The digital mux blocks 3553 are used to multiplex out the data of the respective row registers 3552 into the bus GDAC_DINx, which is applied as an input to the global DAC 3551. The corresponding row S/H buffer 3554 samples the value from the global DAC into the local S/H buffer 3554. Each row has its own respective row register 3552, S/H buffer 3554, and output signal 3555. [00151] During operation, row registers 3552-0 through 3552-n are loaded with digital input bits DINx (where x is the number of bits, such as 8 or 16 bits) for that particular row and receives a clock signal, CLK. The CLK signal is used to load in the data from the digital input bits DINx into the respective row registers 3552. Global digital-to-analog converter 3551 is shared by all rows, and in a time-multiplexed fashion, performs a digital-to-analog conversion on the digital bits DINx stored in a particular row register 3552. The conversion is done by time multiplexing the data of the row registers into the data input (bus GDAC_DINx) of the global DAC 3551. The multiplexing of the row register data into the data input bus GDAC_DINx is enabled by the respective enable signal EN-x 3557-x for each row. The corresponding row sample-and-hold buffer 3554 samples the analog output from global DAC 3551 and holds that value, which is then applied as output signal 3555 for that particular row. Output signal 3555 can be applied, for example, to a control gate line or a word line during a programming operation in that particular row, in the manner described above with respect to other Figures. [00152] Alternatively, a row sample-and-hold buffer 3554 can be shared between multiple rows by time multiplexing the row sample-and-hold buffers. [00153] Figure 36 depicts input block 3600 to be used to provide inputs to VMM array 3401. . Input block 3600 comprises two global DACs 3601-0 and 3601-1; row registers 3602-0 through 3602-n, respectively corresponding to one of the rows numbered 0 through n in the VMM array 3401; digital comparator blocks 3603 through 3603-n respectively corresponding to one of the rows numbered 0 through n in the VMM array 3401; row sample-and-hold buffers 3604-0 through 3604-n, respectively corresponding to one of the rows numbered 0 through n in the VMM array 3401; and output signals 3605-0 through 3605-n, denoted CGIN0, CGIN1…, CGINn-1 and CGINn, respectively, corresponding respectively to one of the rows numbered 0 through n. The digital comparator blocks 3603 compare the value stored in the respective row register 3602 against signal CLKCOUNTx, which signal CLKCOUNTx is a result of a counter which counter counts a clock signal during a predetermined interval. When the digital counting values of the signal CLKCOUNTx matches the contents of the respective row register 3602, the respective row S/H buffer 3604 is enabled to sample the value from the global DAC 3601 into the respective S/H buffer 3604. Each row has its own row register 3602, digital comparator block 3603, and row S/H buffer 3604. [00154] During operation, row registers 3602-0 through 3602-n are loaded with digital input bits DINx (where x is the number of bits, such as 8 or 16 bits) for the associated row and receives a clock signal, CLK. The CLK signal is used to load in the data from the digital input bits DINx into the row registers 3602-x. Global DAC 3601 (which consists of a plurality of global DACs, such as 3601-0 and 3601-1) is shared by all rows. In one example, global DAC 3601-0 operates on even rows and global DAC 3601-1 operates on odd rows. Global DAC 3601 receives a clock signal CLKDAC and output an analog value corresponding to a count of the CLKDAC clock.. Global DAC 3601 performs a digital-to-analog conversion on the digital bits DINx stored in the relevant row register(s) 3602 (through the GDAC_DINx bus). The corresponding row(s) sample-and-hold buffer 3604 for that row(s) samples the analog output from global digital-to-analog converter 3601 and holds that value, which is then applied as output signal 3605 for that particular row. Output signal 3605 can be applied, for example, to a control gate line or a word line during a programming operation in that particular row or rows, in the manner described above with respect to other Figures. [00155] Figure 37A depicts waveforms 3700 that illustrate example voltage levels for outputs CGIN0 and CGIN1, after respective sample-and-hold actions by row sample-and-hold buffer 3504 in Figure 35A, row sample-and-hold buffer 3554 in Figure 35B, or row sample-and-hold buffer 3604 in Figure 36, responsive to GDACsup 3701. The signal GDACsup 3701 is the supplied voltage from the global DAC such as from the global DAC 3501 in Figure 35A, global DAC 3551 in Figure 35B, and global DACs 3601-0 and 3601-1 in Figure 36. GDACsup 3701 is a linear DAC voltage curve, i.e. that global DAC output represents a linear translation of the digital input values to analog values. Such a linear translation is suitable for memory cells operating in the linear region. Signal 3702 shows the sampled voltage value (level) on row 0 (CGIN0) and signal 3703 shows the sampled voltage value (level) on row1 (CGIN1) as examples. Signal DAC_sampling_en 3704 is the control signal enabling the sampling and hold operation. Four examples of sampling are shown at edges 3705, 3706, 3707, and 3708 corresponding to different voltages being sampled. [00156] Figure 37B depicts waveforms 3720 that illustrate example logarithmic voltage levels for outputs CGIN0 and CGIN1, after respective sample-and-hold actions by row sample-and- hold buffer 3504 in Figure 35A, row sample-and-hold buffer 3554 in Figure 35B, or row sample- and-hold buffer 3604 in Figure 36, responsive to GDACsup 3721. The use of a logarithmic translation of the digital input values to analog values is suitable for memory cells operating in the sub-threshold region. Alternatively, it can be used for memory cells operating in the saturation region. The signal GDACsup 3721 is the supplied voltage from the global DAC such as from the global DAC 3501 in Figure 35A, global DAC 3551 in Figure 35B, and global DACs 3601-0 and 3601-1 in Figure 36. GDACsup 3721 is a log DAC curve. Signal 3722 shows the sampled voltage value (level) on row 0 (CGIN0) and signal 3723 shows the sampled voltage value (level) on row1 (CGIN1) as examples. Signal DAC_sampling_en 3724 is the control signal enabling the sampling and hold operation. Four examples of sampling are shown at edges 3725, 3726, 3727, and 3728 corresponding to different voltages being sampled. [00157] An intelligent DAC sampling method is as follows. As shown in Figures 37A and 37B, the sampling enabling is done only on the row registers that are used for a particular input operation, meaning that the sampling is enabled at the first minimum value of the row registers and ends at the maximum value of the row registers. This is to reduce the sampling times to be as needed only basing on the range of the values of the input on the row registers (that is, the values of the activation inputs). [00158] Furthermore, if a maximum number of rows are enabled for sampling at a time, for example maximum of 128 are enabled, so if there are, say, 180 rows enabled for a same input value, the samplings will happen twice, 1 ^st time for 128 rows and the 2 ^nd time for 62 rows, or alternately, 1 ^st sampling time for 90 rows and 2 ^nd sampling times for 90 rows. This is to reduce the loading on the sampling circuit in case large loading may cause undesirable setting time. [00159] Figure 38 depicts input block 3800 to be used with VMM array 3401. Input block 3800 comprises sub- block 3810, SRAM 3418, registers 3801-0, 3801-1, …, 3801-n, and address decoders 3804-0, 3804-1, …, 3804-n. Sub-block 3810 optionally can comprise one of input blocks 3500, 3550, and 3600 from Figures 35A, 35B, and 36, respectively. Sub-block 3810 comprises registers 3802-0, 3802-1, …, 3802-n and row sample-and-hold buffers 3803-0, 3803- 1, …, 3803-n and circuitry in between according to Figures 35A, 35B, and 36, as the case may be. In the instance where sub-block 3810 comprises input block 3500, then registers 3802 comprise row registers 3502 and row sample-and-hold buffers 3803 comprise row sample-and- hold buffers 3504. In the instance where sub-block 3810 comprises input block 3550, then registers 3802 comprise row registers 3552 and row sample-and-hold buffers 3803 comprise row sample-and-hold buffers 3554. In the instance where sub-block 3810 comprises input block 3600, then registers 3802 comprise row registers 3602 and row sample-and-hold buffers 3803 comprise row sample-and-hold buffers 3604. [00160] Address decoders 3804 receive an address for a data-in load operation to load the data into the registers 3802 or the registers 3801. The data is such as activation data or input data such as from an object or image to be classified or recognized in a neural network application. It outputs a signal enabling the registers 3801 or registers 3802 indicating which registers are asserted for data in load operation. The data in (not shown) typically varies from 8-256 bits. [00161] Address decoders 3804 also receive an address for a read-verify or program operation and outputs a signal to registers 3801or registers 3802 indicating which row or rows are asserted for the read-verify or program operation. Read-verify is a read operation that is used in weight tuning, where a cell is programmed to a target current representing a target weight in a neural network and then the cell current is verified to ensure it approximates the target current during weight tuning algorithm. [00162] Registers 3802 enable row sample-and-hold buffers 3803 using activation data stored in each such register. In an example implementation, there might be 1024 rows and 1024 instances of register 3802, where 8 bits of activation data are stored in each register 3802. [00163] To load data for the register 3802, the number R of clock cycles needed is R = number of rows x 8 (for 8 bits of activation data) and divided by the data in width, e.g., 16 bits data in (e.g., R = 1024*8/16 = 512). [00164] Registers 3801 comprise one register coupled to and associated with each register 3802. Each register 3801 is loaded with activation data for its associated register 3802, which can be performed sequentially over R clock cycles. Thereafter, during a first clock cycle, the data from each register 3801 is loaded into its associated register 3802 in parallel. Thus, the registers 3802 are loaded from the respective registers 3801 in parallel in a single time period instead of serially in R clock cycles. This vastly speeds up the timing for the data in load operation. [00165] Optionally, SRAM 3418 can be used to load all registers 3802 sequentially during R clock cycles as a background operation. [00166] Optionally, SRAM 3418 is used to load registers 3801 sequentially with its data. Figure 38B depicts input method 3850 that can be performed using input block 3800 of Figure 38A. The first operation is outputting, by a plurality of address decoders, a plurality of row enabling signals in response to an address (3851). The next operation is storing sequentially, by a first plurality of registers, activation data in response to the plurality of row enabling signals (3852). The storing sequentially optionally comprises receiving the activation data by the first plurality of registers from a static random access memory. The next operation is storing in parallel, by a second plurality of registers, activation data received from the first plurality of registers (3853). The next operation is driving, by a plurality of row sample and hold buffers, rows of an array of non-volatile memory cells during a read neuron operation in response to activation data received from the second plurality of registers (3854). [00167] Figure 39A depicts input block 3900. Input block 3900 comprises sub-block 3910, VMM array 3401, and address decoders 3904-0, 3904-1, …, 3904-n. Sub-block 3910 optionally can comprise one of input blocks 3500, 3550, and 3600 from Figures 35A, 35B, and 36, respectively. Sub-block 3910 comprises row registers 3902-0, 3902-1, …, 3902-n and row sample-and-hold buffers 3903-0, 3903-1, …, 3903-n and circuitry in between according to Figures 35A, 35B, and 36, as the case may be. In the instance where sub-block 3910 comprises input block 3500, then row registers 3902 comprise row registers 3502 and row sample-and-hold buffers 3803 comprise row sample-and-hold buffers 3504. In the instance where sub-block 3910 comprises input block 3550, then row registers 3902 comprise row registers 3552 and row sample-and-hold buffers 3903 l comprise row sample-and-hold buffers 3554. In the instance where sub-block 3910 comprises input block 3600, then row registers 3902 comprise row registers 3602 and row sample-and-hold buffers 3903 comprise row sample-and-hold buffers 3604. [00168] Address decoders 3904 receive an address for a data-in load operation to load data (not shown) into the row registers 3902. The data is such as activation data or input data such as from an object or image to be classified or recognized in a neural network application. It outputs a signal enabling row registers 3902 indicating which registers are asserted for data in load operation. The data in (not shown) typically varies from 8-256 bit. [00169] Address decoders 3904 may also receive an address for a read-verify or program operation and outputs a signal to row registers 3902 indicating which row or rows are asserted for the read-verify of program operation. In this example, each row register stores activation data (e.g., 8 bits of activation data) as well as a tag bit or a plurality of tag bits such as one for row enabling and another for row DAC sampling. For example, row register 3902-0 comprises tag bit 3905-0, row register 3902-1 comprises tag bit 3905-1, row register 3902-n comprises tag bit 3905-n, and so forth. Tag bit (row enable tag bit) 3905 is used for row enabling to disable the activation input data stored in the row register regardless of whether the row is selected or not selected by address decoder 3904. For example, if tag bit 3905-0 of row 0 has a certain value (e.g., a “1” value), the activation data in row register 3902-0 is output. If tag bit 3905-0 has a different value (e.g., a “0” value), the activation data in row register 3902-0 will not be output and row S/H buffer 3903-0 will receive a Z state from row register 3902-0. Another tag bit (row S/H tag bit) is used for row DAC sampling to enable or disable the sampling of the global DAC value into the local row S/H buffer 3903. [00170] Figure 39B depicts input block 3920. Input block 3920 is similar to input block 3900 except that it contains a second set of row registers (shadow registers) 3906-0, 3906-1, …, 3906- n, each containing a respective tag bit(s) 3907-0, 3907-1, …, 3907-n. Each row can toggle between row register 3902 and row register 3906. For example, during one operation, address decoder 3904 provides an output to row register 3902 and during another operation, address decoder 3904 provides an output to row register 3906. For example, during one operation, row register 3902-0 outputs data if tag bit(s) 3905 is enabled, and during another operation, row register 3906 outputs data if tag bit 3907 is enabled. This toggling can be implemented by multiplexors (not shown) or other control logic. In this manner, one set of row registers 3902 or 3906 can be loaded with activation data while the other set is being used to actively output its activation data according to signals from address decoder 3904. [00171] Figure 39C depicts input block 3940. Input block 3940 is similar to input block 3900 except that it contains a second set of row registers 3908-0, 3908-1, …, 3908-n, each containing a respective tag bit(s) 3909-0, 3909-1, …, 3909-n. Each row can toggle between row register 3902 and row register 3908. For example, during one operation, address decoder 3904 provides a signal to row register 3902 and during another operation, address decoder 3904 provides an output to row register 3908. For example, during one operation, row register 3902 outputs data if tag bit(s) 3905 is enabled, and during another operation, row register 3908 outputs data if tag bit(s) 3909 is enabled. This toggling can be implemented by multiplexors (not shown) or other control logic. In this manner, one set of row registers 3902 or 3908 can be loaded with activation data while the other set of row registers is being used to actively output its activation data according to signals from address decoder 3904. [00172] Figure 39D depicts input block 3960. Input block 3960 is similar to input block 3940 except that it contains a second set of row sample-and-hold buffers 3911-0, 3911-1, …, 3911-n for the same array input (e.g., CGINx). Each row can toggle between row register 3902 and row register 3908. For example, during one operation, address decoder 3904 provides a signal to row register 3902 and during another operation, address decoder 3904 provides an output to row register 3908. Similarly, during one operation, row register 3902 outputs data according to tag bit(s) 3905, and during another operation, row register 3908 outputs data according to tag bit(s) 3909. Each row can toggle (using control signals, not shown) between row S/H buffer 3903 and row S/H buffer 3911. This toggling can be implemented by multiplexors (not shown) or other control logic. In this manner, one set of row registers 3902 or 3908 can be loaded with activation data while the other set is being used to actively outputs its activation data according to signals from address decoder 3904. [00173] In one example, first activation data and first tag bits are loaded into row registers 3902 and second activation data and second tag bits are loaded into row registers 3908. First activation data and second activation data can be either identical or different, and first tag bits and second tag bits can be either identical or different. [00174] Figure 40A depicts output block 4000. Output block 4000 receives output current from VMM array 3401 (not shown), typically from bit lines or source lines of VMM array 3401. Output block 4000 comprises current-to-voltage converter 4001, analog-to-digital converter 4002, output register 4003, and output register 4004. Current-to-voltage converter 4001 converts current received from VMM array 3401 into respective voltages, whose value reflects the value of the current received from VMM array 3401. Analog-to-digital converter 4002 converts those respective voltages into bits representing the value of the voltage received from the respective current to voltage converter 4001, which therefore reflects the value of the current received from VMM array 3401. The bits are then stored in output register 4003 or output register 4004. Output operations can toggle between output register 4003 and output register 4004. For example, during a first operation during a first time period (e.g., one or more clock cycles), output data is loaded into output register 4003. During a second operation during a second time period (e.g., one or more clock cycles) after the first time period, that data is read out from output register 4003 by another device in the system, while new output data is loaded into output register 4004. During a third operation during a third time period (e.g., one or more clock cycles) after the second time period, that new output data is read out from output register 4004 by another device in the system, and optionally, output data can be loaded into output register 4003 and the sequence is repeated. This decreases the amount of latency associated with output operations, as data can be read by the external device from a first output register concurrently with other data being loaded into the other output register.Optionally, Output block 4000 optionally comprises column tag bits 4005 to enable the current-to-voltage converter 4001 and analog-to-digital converter 4002. Column tag bits 4005 can comprise a column tag bit for each column in VMM array 3401. Column tag bit 4005 loading is similar to row tag bit loading discussed above with reference to Figures 39A to 39D. The function of the column tag bit is similar to the function of the row tag bit discussed above with reference to Figures 39A to 39D. For example, current-to-voltage converter 4001 and analog-to-digital converter 4002 can be configured to output data for a column when the column tag bit 4005 for that column has a first value and it not output data when the column tag bit has a second value. [00175] Figure 40B depicts output block 4020. Output block 4020 is the same as output block 4000 with the addition of accumulator 4021. Accumulator 4021 can sum the values received from current-to-voltage converter 4001, analog-to-digital converter 4002, output register 4003, and output register 4004 over a certain time period. This can be useful, for example, if a neural read operation is performed on VMM array 3401 in a time-multiplexed manner, for example, by reading half of the rows during a first time period and the other half of the rows during a second time period. Outputs from the first time period can be received by output register 4003, and outputs from the second time period can be received by output register 4004, and accumulator can sum the values received from output register 4003 and output register 4004. [00176] Output block 4000 optionally comprises column tag bits 4005 to enable the current- to-voltage converter 4001 and analog-to-digital converter 4002. Column tag bits 4005 can comprise a column tag bit for each column in VMM array 3401. Column tag bit 4005 loading is similar to row tag bit loading discussed above with reference to Figures 39A to 39D. The function of the column tag bit is similar to the function of the row tag bit discussed above with reference to Figures 39A to 39D. For example, current-to-voltage converter 4001 and analog-to- digital converter 4002 can be configured to output data for a column when the column tag bit 4005 for that column has a first value and it not output data when the column tag bit has a second value. [00177] Figure 40C provides an example circuit for output accumulator 4021. Output accumulator receives data from current-to-voltage converter 4001, analog-to-digital converter 4002, output register 4003, and output register 4004. The data is received by shifter 4042, which performs a shift function in response to EN_SHIFT. The output of shifter 4042, D1, is provided to adder 4043, which adds D1 to D2, which it also receives and is enabled by EN_ADD. The output of adder 4043 is provided to accumulator register 4044, which stores the output of adder 4043 and provides it back to adder 4043 as D2 for the next add operation. In this manner, the output of current-to-voltage converter 4001, analog-to-digital converter 4002, output register 4003, and output register 4004 can be added over a time period. [00178] Shifter 4042 is used, for example, during a serial input (DAC) mode, in which one bit of the activation input is read at a time, and where the amount of shit of the output bits depends on the binary position of the input bit. For example, the LSB (least significant bit) of the input bits results in no shift in the output, the (LSB+1) input bit has results in a 1-bit shift left, the (LSB+2) input bit results in a 2-bit shift left, etc., and where this read operation is performed 8 times for an 8-bit activation input. The final output from accumulator register 4044 is the result of the entire 8-b activation input. [00179] Figure 41 depicts waveforms 4100 for a first phase 4101 where row registers are loaded with activation data, and a second phase 4102 where a neural read operation is performed using that activation data. [00180] Figure 42 depicts waveforms 4200 for a random access read operation 4201. [00181] Figure 43 depicts waveforms 4300 for a burst read operation 4301. [00182] Figure 44 depicts waveforms 4400 for a neural read operation 4401. [00183] Figure 45 depicts neural read operation 4500. Neural read operation 4500 begins (4501). Activation data is loaded into row registers (4502). Next a group of N rows is enabled (4503). Next, the column address is input (4504). A read operation is performed (4505), which involves the DAC sampling as shown in Fig 37A and 37B (which utilizes the circuits shown in Figures 35A-B, 36, 38, and 39A-39D) and (bitline) output circuit 3407 (which will convert current into voltage using an ITV and convert the voltage into a digital output using an ADC) in Figure 34, where the output data is a digital output from an ADC. Data is loaded into the output register (4506). The system determines if another column address needs to be read. If yes, it returns to operation 4504. If not, then the system determines if another group of N rows needs to be read (4508). If yes, it returns to operation 4503. If no, then the neural read operation is done (4509), at which point the data out optionally is shifted out (4510) or the neural read operation is over. Per neural read operation, for a groups of rows with column switching, the neural read time is 1 row DAC latency + N of ITV+DAC latency with N column multiplexing. For example, if DAC latency is 2µs and ITV+ADC latency is 1µs, then time to read an entire row is 1 x (DAC latency) + 16 x (ITV +ADC latency) = 18µs. Basically, for next column neural read, the DAC latency does not contribute any additional time. [00184] Figure 46 depicts neural read operation 4600. Neural read operation 4600 begins (4601). Activation data is loaded into a first set of row registers (4603). Activation data is then loaded into a second set of row registers (4602). Concurrent with that event, the column address or row group is changed (4604). A read operation is performed (4605). Output data is loaded into the output register (4606). If the read operation is not done (4607), the process returns to operation 4604. If the read operation is done, then the system (using a logic controller, not shown) determines if it needs to load data from the second set of row registers into the first set of row registers (4608). If no, then neural read operation is done (4611). If yes, then data is loaded from the second set of row registers into the first set of row registers (4609). The system then determines if the neural read operation is done (4610). If yes, then neural read operation is done (4611). If not, then it returns to operation 4604. [00185] Figure 47 depicts neural read operation 4700. First, activation data is loaded into a first set of row registers (4701). Activation data is then loaded into a second set of row registers (4702). Concurrent with that event, the column address or row group is changed (4703). A read operation is performed (4704). Data is loaded into the output register (4705). If the read operation is done (4706), then the system proceeds to operation 4707. If not, the system returns to operation 4703. In operation 4707, the system determines if the second set of row registers and its corresponding row S/H buffers are enabled. If yes, then the operation is done (4708). If no, the second set of row registers and their corresponding row S/H buffers are enabled and the system returns to operation 4703 to continue the neural read operation. [00186] Figure 48 depicts read out operation 4800. Previously, digital output data has been loaded into output register 1 or output register 2. Output data is then shifted out from output register 1 or output register 2 (4801). [00187] Figure 49 depicts neural read operation 4900. First, activation data is loaded into row registers (4901). Data is then shifted out from output register 1 or output register 2 (4902). Concurrent with that event, the column address or row group is changed (4903). A neural read operation is performed (4904). Data is loaded into the output register 1 or output register 2 (4905). If the neural read operation is done (4906), then the operation is done (4907). If not, then the system returns to operation 4903 to continue the neural read operation. [00188] It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed therebetween) and “indirectly on” (intermediate materials, elements or space disposed therebetween). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.