Matching Bandwidth of an LNA

CROSS REFERENCE TO RELATED APPLICATIONS

[0001 j The present application is related to the co-filed U.S. application entitled "An injection Locked Divider with Injection Point Located at a Tapped inductor" both fil ed on December 6, 201 1 , which are invented by the same inventor as the present application and incorporated herein by reference in their entireties.

BACKGROUND OF THE INVENTION

[0002] The Federal Communications Commission (FCC) has allotted a spectrum of bandwidth in the 60GHz frequency range (57 to 64GHz). The Wireless Gigabit Alliance (WiGig) is targeting the standardi ation of this frequency band that will support data transmission rates up to 7 Gbps.

Integrated circuits, formed in semiconductor die, offer high frequency operation in this millimeter wavelength range of frequencies. Some of these integrated circuits utilize Complementary Metal Oxide Semiconductor (CMOS), Silicon-Germanium (SiGe) or GaAs (Gallium Arsenide) technology to form the dice in these designs. At 60GHz, the interface issues between the LNA and the mi er are presented.

[0003] CMOS (Complementary Metal Oxide Semiconductor) is the primary technology used to construct integrated circuits. -channel devices and P-channel devices (MOS device) are used in this technology which uses fine line technology to consistently reduce the channel length of the MOS devices. Current channel lengths are 40 nm, the power supply of VDD equals 1.2Vand the number of layers of metal levels can be 8 or more.

[0004] Cost is a drivi ng force in electronic products. Integration of circuit has allowed many more devices into the die. In addition, massive computation is typically requires when operating wireless systems. This has forced analog designers to introduce their circuit techniques into 8 layer metal CMOS processes more geared for digital logic manipulation rather than analog functions. The design of high speed analog circuifs (60 GHz) in the S layer 40 nm CMOS process is a difficult task thai requires innovation, careful design and analysis.

[0005] Conventional techniques in high frequency circuit design can unnecessarily waste energy. Any technology being pushed to the limit, as in the design of 60 GHz receiver frond-ends thai includes an LNA (Low Noise Amplifier) and mixer, makes these energy losses more pronounced. These losses influence target objectives and can cause the chip or die to fail meeting the

specifications. New circuit techniques are required to reduce these energy losses and allow the circuit to achieve 60Ghz operation in the WiGig specification.

BRIEF SUMMARY OF THE INVENTION

[0006] Various embodiments and aspects of the inventions will be described with reference to details discussed below, and the accompanying drawings will illustrate the various embodiments. The following description and drawings are illustrative of the invention and are not to be construed as limiting the invention. Numerous specific details are described to provide a thorough

understanding of various embodiments of the present invention. However, in certain instances, well- known or conventional details are not described in order to provide a concise discussion of embodiments of the present inventions.

[0007] One of the embodiments of the disclosure is a common source LNA interfacing to a mixer where the mixer responds to input current signals generated by the output of the LISA. An output signal spectrum is developed across the resonant circuit load of the LNA and is coupled to a mixer. The signal spectrum of the input signal is amplified and generates an output signal spectrum that is carried within the current signals being applied to the mixer. The voltage output of the L A's load is translated to a current output that is applied to the input of the mixer. These input current signals apply the energy associated with the current directly into the mixer to minimize the overall power dissipation. [0008] Another embodiment uses a series peaking inductor coupling the cascode devices of the LNA together. The area occupied by the inductors are orders of magnitude larger that the area occupied by the devices in the LNA. A device represents a CMOS transistor where the transistor can be either P or N-type channel transistor, lit addition, the physical displacement between the upper cascode device and the lower cascode device of the LNA can he quite large. A series peaking inductor formed from a wide metal layer is used to couple the drain of the lower cascode device to the source of the upper cascode device. A capacitance can be added to the wide trace of the inductor to form a bandpass filter in order to pass those frequencies of interest.

[0009] Another embodiment of the invention is the adjustment of the width of the top cascode device with respect to the width of the bottom input device in the cascode L to adjust the optimum (NF) Noise Figure and the center frequency of the resonant circuit to the desired frequency of operation. The NF can be further improved O. kkiB by reducing the width of the upper cascode device below the width of the lower cascode device, hi addition, the center carrier frequency of the LNA is decreased.

[0010] An additional embodiment uses the impedance of the mixer to reduce the Q (or quality factor) of the resonant circuit. By reducing the Q, the bandwidth of the receiver is increased. The adjustment of the width of the top cascode device and the load of the impedance of the mixer reduces the Q and eliminates the need for either a capacitive or resistive array to perform this function thereby reducing the introduction of unnecessary parasitic elements. This allows the receiver to meet the requirements for the VViGig initiative at a reduced power.

BRIEF DESCRIPTION OF THE DRAWINGS

[001 1 J Please note that the drawings shown in this specification may not necessarily be drawn to scale and the relative dimensions of various elements in the diagrams are depicted schematically. The inventions presented here may be embodied in many different forms and should not be

construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this di sclosure will be through and complete, and will, fully convey the scope of the invention to those skilled in the art. In other instances, well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiment of the invention. Like identifiers or numbers refer to like elements in the diagrams.

[0012] FIG. la depicts a. common source device stage in accordance with the present invention.

[0013] FIG. lb shows a high frequency model of the common source MOS device in accordance with the present invention

[0014] FIG, 2a illustrates a common gate device stage in accordance with the present invention.

[0015] FIG. 2b shows a. high frequency model of the common gate MOS device in accordance with the present invention.

[0016] FIG. 3a presents a common source device stage with a cascode structure in accordance with the present invention.

[0017] FIG. 3b shows a common gate device stage with a cascode structure in accordance with the present invention.

[0018] FIG. 3c presents block diagram of the LN A in accordance with the present i nvention.

[0019] FIG. 4a illustrates a common source device stage with a cascode structure using a peaking inductor in accordance with the present invention.

[0020] FIG. 4b shows a common gate device stage, with a cascode structure using a peaking inductor in accordance with the present invention.

[0021 ] FIG. 4e depicts a common source device stage with a cascode structure using a peaking inductor and a switched resistive array to adjust the bandwidth of the resonant circuit in accordance with the present invention. [0022] FIG. 4d presents a common gate device stage with a cascode structure using a peaking ifHiuctor and a switched resistive array to adjust the bandwidth of the resonant circuit in accordance with the present invention.

[0023] FIG. 4c depicts a common source device stage with a cascode structure using a peaking inductor and a switched capacitive array to adjust the center frequency of the resonant circuit, in accordance with the present invention.

[0024] FIG, 4f shows common gate device stage with a cascode structure using a peaking inductor and a switched capacitive array to adjust the center frequency of the resonant circuit in accordance with the present invention.

[0025] FIG. 5a presents the graphical results of the Noise Figure of an LNA for two different width ratios of the upper cascode device to the lower cascode device versus frequency o WCS (Worst Case Slow) operation in accordance with the present invention,

[0020] FIG. 5b illustrates the graphical results of the Noise Figure of an LNA for two different widths of the upper cascode device to the lower cascode device versus frequency of BCF (Best Case

Fast) operation in accordance with the present invention.

[0027] FIG. 5c presents the graphical results of the forward gain of an LN A for two different widths of the upper cascode device to the lower cascode device versus frequency of WCS (Worst

Case Slow) operation in accordance with the present invention.

[0028] FIG. 5d illustrates the graphical resul ts of the forward gain of an LNA for two different widths of the upper cascode device to the lower cascode device versus frequency of BCF (Best. Case Fast) operation in accordance with the present invention.

[0029] FIG. 6a shows a portion of a. conventional Gi bert mixer. [0030] FIG. 6b ilkssirates a block diagram of the L A, Quadrature osciliator and I and Q mixers in accordance with the present invention.

[003 1] FIG. 7 a presents the circuit of the LNA, Quadrature oscillator outputs and I and Q mixers in accordance with the present invention.

[00 2] FIG. 7b depicts the measured gain response of the common source LNA, Quadrature oscillator outputs and I and Q mixers in accordance with the present invention.

[0033] FIG. 8a illustrates the physical layout of the inductors and devices in the LN A in accordance with the present invention.

[0034] FIG. 8b illustrates the cross sectional view along A-A' in FIG. 8a in accordance with the present invention,

[0035] FIG. 8c presents a via stack in the CMOS process in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0036] The inventions presented in this specification can be used in various high, frequency system designs. Some of the basic circuits for an analog amplifier include the common source and common gate structures as illustrated in FIG. la and FIG. 2a, respectively. The common source

configuration of a LNA (Low Noise Amplifier) in FIG. la illustrates a voltage source 1-2, a voltage in series with a resistor, that can represent the output of an antenna or another source of an extracted signals. The output 1-1 of th voltage source 1-2 couples to the input of the gate of Mj by the gate inductance Lj. The voltage source 1-2 provides the input frequency spectrum to the receiver. The source of Mj is coupled to ground by the inductor Lj. At DC, the impedance of the inductor Lj is zero causing the source of j to be coupled to ground (G D or VSS). This configuration is known as the common source. The drain of device M _:i is coupled to V D by a load 1-3, i this case, the inductor L3 and the output outj is provided at the drain of Mj [0037 J A small signal model of the common source is provided in FIG. lb. The gate (g), source (s) and drain (d) of the device are labeled. Between the gate and source is the gate to source capacitance A current source gmV* between the source and drain is controlled by the voltage between the gate and source V _ss . The input is applied at 1-1 while the output is provided at. outj. The voltage source and any parasitic resistances (for example, the resistance of the inductors) and several of the capacitances known in the art. (i.e. C _e ,t) are not illustrated to simply the diagram. Finally, the load on the drain of the device is the parallel combination of the capacitance. j, at the drain and the inductance L3 which is a resonant circuit 1-4. The resistance, not illustrated, is in parallel with the capacitance and inductance completing the parallel R.LC tank circuit or resonant circuit of the LNA. The load or resonant circuit for the remaining cases of the L A's are similar and will generally not be explicitly shown,

[0038] The common gate configuration of a LNA in FIG. 2a illustrates a voltage source 1-2, a voltage in series with a resistor, that can represent the output of an antenna or another source of an extracted signal also called the input signal spectrum. The voltage source 1-2 couples to the source 2-1 of j The source is coupled to ground by the inductor L§. The gate of M2 is coupled to an AC ground by the capacitor C? and to the power supply VDD by the inductor L At DC, the impedance of the inductor L is zero causing the gate of M2 to be coupled to a power supply (VIXD). in general the inductance of L* can be minimized, and in some cases, the inductor ^' L4 can be replaced by a short. The configuration in FIG. 2a is known as the common gate. The drain of device M ₂ is coupled to VDD by the inductor J . The output of the circuit is available at out*.

[0039] A small signal model of the common gate is provided in. FIG. 2b. The gate (g), source (s) and. drain (d) of the device are labeled. The input is applied at 2-1 while the output is provided at outj. Between the gate and source is the gate to source capacitance C^. A current source g„, V' _gs between the source and drain is controlled by the voltage between the gate and source V _gs . The inductor Ls is between the source and ground. The voltage source and any parasitic resistances (for example, the resistance of the inductors) and several of the capacitances known in the art (i.e. C^) are not illustrated to simply the diagram . Finally, the load on the drain of the device is the parallel combination of the capacitance, Cj, at the drain and the inductance L«. FIG 2b illustrates that the current gai n of the common gate approaches one. [0040] FIG. 3a presents a cascode common gate structure. The cascode structure comprises the two stacked devices, M ₄ and M _¾ and couples to VSS and VDD through the inductors, .1* and L¾.

Typically, these inductors can occupy an area 50uro on a side while the devices ca be incorporated into an. area of Sum on a aide The area occupied by these inductors compared to the area occupied by the devices can be two orders of magnitude larger. This illustrates that the placement of the inductors play a very important role in determining just how close the devices in the cascode structure can be placed next to one another. The input is applied at hij through the inductor L? to the gate of M while the output is provided at outs. Quite often, the two devices of the cascode cannot be placed next to each other. Thus, a metal interconnect may be required to couple the drain of to the source of Mj. This interconnect is represented by the resistance Rj. This resistance introduces losses and can decrease the gain of the circuit.

[00411 In FIG, 3 a, the cascode structure provides several advantages including; better isolation between input and output nodes, a high output impedance, and a higher bandwidth, A current mirror is formed by devices MM and M ₄ controlled by I««s _f . The resistor Mi acts as a low pass filter to stabilize the voltage from the diode connected device MM and applies the voltage to the gate of device M». The device M* is configured in a common source configuration while the device M3 is in a common gate configuration. The voltage at node 3-1 is nearly constant reducing the miller feedback capacitance for the device M . Because the miller capacitance is reduced in this circuit, the cascode configuration allows a higher bandwidth.

[0042] FIG. 3b presents a cascode common gate structure. The cascade structure comprises the two stacked devices, M ₆ and Ms, and couples to VSS and VDD through the inductors, Lu and L _t2 . A current mirror is formed by devices M _h2 and M« controlled by ¼,{ _β»2 - ^" The resistor R ₂ acts as a low pass filter to stabilize the voltage from the diode connected device M an applies the voltage to the gate of device M*. As mentioned earlier, the placement of the inductors pla a very important role in determining just how close these devices in the cascode structure can be placed next to one another. Quite often, these devices cannot be placed next to each other. Thus, a metal interconnect, modeled by the resistor R4, couples the drain of M$ to the source of Mg. This interconnect is represented by the resistance R . [0043] in FIG. 3b, the input is applied at in ₄ through the inductor Lj« to the source of while the output is provided at out*. In general the inductance of Ln can be minimized, and in some cases, the inductor Lie can be replaced by a short. The cascade structure provides several advantages including; better isolation between input and output nodes, a high output impedance., and a higher bandwidth. The device M$ is configured as a common gate white the device M3 is also in a common gate configuration This circuit can provide a current gain approaching one.

[0044] FIG 3c illustrates the block diagram of the LNA, A signal "from a source" that could be an antenna, the electrical output of a fiber network, or a very weak signal is amplified by the LNA and provided at its output out. The LNA is optimized to keep the noise figure low while also providing a gain to the weak signal

[0045] FIG. 4a presents a second cascode common source structure. The cascode structure comprises the two stacked devices, !V¾ and M _7j and couples to VSS and ^' VDD through the

inductors, L| and Lis. A current mirror is formed by devices M and controlled by Iwass and applied to the gate of device Ms. The resistor Rs acts as a low pass filter to stabilize the voltage from the diode connected device ». The area occupied by the inductors can be two orders of magnitude larger than the area occupied by the devices. Often these two devices cannot be placed next to each other. Thus, a metal interconnect is used to couple the drain of »io the source of M. . This interconnect, if modeled as a resistor, can decrease the gain of the circuit. By increasing the width of this metallic interconnect the resistance is decreased at the expense of increased capacitance. However, another feature of this interconnect becomes more prominent: its self- inductance, L Thus, FIG, 4a illustrates the substitution of the resistor model of R3 in FIG. 3a by the inductor Li«. This inductance can now be used as a peaking inductor which resonates with the corresponding capacitance of the interconnect and devices l oading this interconnect. The function of the peaking inductor and capac ve load forms a band-pass filter which is adjusted to operate at 60GHz. Thus, although the placement of the two cascode devices are displaced from one another on the die, the peaking inductor can minimize the loss of the resistive component in the interconnect between the cascode devices and provide a band-pass function. [0047] In FIG. 4a, the in ut is applied at iiis and arrives at the gate of Ms through the inductor L _J4 while the output is provided at oot$. In general, the inductance of LM can be minimized, and in some cases depending on the layout, the inductor Lu can he replaced by a short. A current mirror is formed by devices M» and M _s controlled by ^' hbxa. The cascode structure provides several advantages including; better isolation between input and output nodes, a high output impedance, and a higher bandwidth. The device M ₈ is configured as a common source while the device M _? is i n a common gate configuration.

[0046] FIG, 4b presents a cascode common gate stmcture. The cascade structure comprises the two stacked devices, Mi« and Μ· , and couples to VSS and VDD through the inductors, Li? and A. current mirror is formed by devices M _¾ and Mjo controlled by l _$4 > The resistor R ₆ acts as a low pass filter to stabilize the voltage from the diode connected device MM. AS mentioned earlier, the placement of the inductors play a very important role in determining just how close these devices in the cascode structure can be placed next to one another. Quite often, these devices cannot be placed next to each other. The interconnect, if modeled as a resistor, can decrease the gain of the circuit By increasing the width of this metallic interconnect, the resistance is decreased at the expense of increased capacitance. However, as before, another feature of this interconnect becomes more prominent: its self-inductance, L ₂₀ Thus, a metal interconnect, previously modeled as a resistor * in FIG. 3b, is now modeled as the inductor Lao. This inductance can now be used as a peaking inductor which resonates with the corresponding capacitance of the interconnect and devices loading this interconnect. Thus, although the placement of the two cascode devices are displaced from one another on the die, the peaking inductor can minimize the loss of the resistive component, in the interconnect between the cascode devices and provide a band-pass function that can be adjusted to operate at 60GHz.

[0047] In FIG, 4b, the input i s applied at i * and arrives at the source of Mjo through the inductor Lis while the output is provided at out*,. In general, the inductance of Lis can be minimized, and in some cases depending on. the l yout, the inductor Lis can be replaced by a. short. A current minor is formed by devices M and ¾½ controlled by ms4 The cascode structure provides several, advantage including; better isolation between input and output nodes, a high output impedance, and a higher bandwidth. The device Μ _:!0 is configured as a common gate while the device M<» is a!so in a common gate configuratio

[0048] Ideally, the LNA would like to pass all frequencies equally over the targeted spectrum range from 57Ghz to 64GHz and block all other frequencies. However this condition is very difficult to achieve. Typically, a resonant circuit (comprising an inductor, capacitor and resistance) is also known as an RLC tuned circuit. The response of a resonant circuit is measured near the center frequency e> _s of the RLC resonant circuit. The bandwidth B is given as B =(« _C )/Q. The term Q is known as the quality factor.

[0049] As Q is decreased, the bandwidth of the resonant circuit increases while the gain decreases. This allows a resonant circuit to be adjusted so the bandwidth covers the desired spectrum range and the L A can amplify any signal within the bandwidth, but the gai of the LNA lias been decreased while the noise increased. O the other hand, as Q is i ncreased, the bandwidth of the resonant circuit decreases while the gain increases. This creates a very selective bandpass circuit where only a portion of the desired spectrum would be captured.

[0050] The resistance R in the parallel RLC resonant circuit can control the value of Q according to

the relation Q The parasitic portion of R in FIG. 4c is given by R _a plus any dynamic resistance that are switched into the resonant circuit, while the parasitic capacitance C is given by C _» . As the R decreases, Q decreases. A resistive array formed by R? and R$ can be switched into the RLC resonant circuit by enabling switches Si and Si (as shown by the arrows) to provide a dynamic resistance adjustment to the RLC resonant circuit in FIG. 4c. The switch Si or S% can be an MOS device that is enabled (to provide a path) and can couple the resistance of R? or Rs into the parallel RLC resonant, circuit. When the resistive array is enabled to place either or both R? or ¾ in parallel with R», the resistance of the resonant circuit decreases and decreases the Q thereby Increasing the bandwidth.

[0051 ] The common gate cascade LNA is illustrated in FIG. 4d. The parasitic capacitance C of the parallel RLC resonant circuit is given by C¾. The parasitic portion of R is given by R¾ in parallel with the two enabled switches S3 and $ ₄ coupli g R> or R _itt into the resonant circuit. The switches 3 and S become disabled (as shown by the arrows) to provide a dynamic resistance adjustment to the RLC resonant circuit in FIG. 4d. The resistors R» and Rj _¾ are removed from being in in parallel with Rj, causing the R in the RLC resonant, circuit to increase. As the R increases, Q increases causing the bandwidth of the resonant circuit to decrease. Although only two resistors with two switches have been show, the number of switches and resistors can greater than two. in some cases, the resistance of the MOS devices forming the switches can provide the resistance while, in addition, the weight of the resistors can be binary weighted in value.

[0052] The capacitance C in the RLC resonant circuit can control the value of© _t . _: if R is very small or can be neglected, according to the relation ω ₀ = ,™. Increasing C, decreases © _c and vice versa. A capacitor array formed by C and Cs can be switched into the parallel RLC resonant circuit by enabling switches S ₅ and S _{i (as shown by the arrows) to provide a dynamic capacitance adjustment to the RLC resonant circuit, in FIG. 4e. The parasitic portion of C the RLC resonant circuit is given by C _a while the resistance R is given by the parasitic values R _¾ . The capacitive switching array of the common source in FIG. 4e is provided by the two disabled switches S$ and $6 that can be enabled to place either or both or Cs in parallel with C _A causing C to increase which decreases the © _« . The center frequency is then shifted to lower frequencies.

[0053] The common gate cascade LNA is illustrated in FIG. 41 The capacitive switching array of the common gate is provided by the two enabled switches S? and Se that can be disabled (as shown by the arrows) to remove either or both C« or C? from being in in parallel with C _k causing the C in the RLC resonant circuit to decrease which increases the _t . The center frequency is shifted to higher frequencies. Although only two capacitors with two switches have been show, the number of switches and capacitors can be varied while the weight of the capacitors can be binary weighted in value. Inserting removing the capacitors by switch enablement/disablement provides the dynamic portion of the C in the RLC resonant circuit in FIG. 4e (common source) and FIG.4f (common gate). Similar elements that have been identified with the same label in FIG. 4a, FIG. 4c and FIG. 4e are similar components while those with the same label in FIG. 4b, FIG. 4d and FIG. 4f are similar components. [0054] The capacitive arrays occupy an area which introduces undesired capacitance into the network The parasitic capacitances of the array elements i ntroduces a dynamic capacitance C _< t that can be comparable to the parasitic capacitance C ₈ of the resonan circuit causing the center frequency ω _€ - ί / (L(C _a + C _d }) to be controlled by the both terms Q and C This additional dynamic capacitance can prevent the LNA from reaching the target frequency of 60GHz. Similarly, the resistive arrays also introduce undesired parasitic capacitances because of their physical layout in the die. Thus, this parasitic capacitance introduced by the use of either the resistive or capacitive array makes the tuning or adjusting of t e bandwidth and center frequency of the LC resonant circuit more difficult for the WiGtg bandwidth. The additional dynamic capacitance introduced into the parallel resonant circuit will make it more difficult for the circuit to operate at 60GHz. A different inventive approach of adjusting the bandwidth and center frequency will be required.

[0055] One inventive approach in an attempt to overcome this barrier is to remove the capacitive array in FIG. 4e and the resistive array in FIG. 4c altogether thereb eliminating the additional dynamic capacitance of their layout. The requirement to adjust the bandwidth and center frequency of the RLC resonant circuit will be adjusted using two innovative embodiments.

[0056] The first innovative adjustment involves sizing the width of the upper cascade device while maintaining the lower cascade device at the same width. This adjustment of the upper cascade transistor width causes the center frequency of the parallel resonant RLC circuit to shift. As the width of the upper cascade device is decreased relati e to the Sower cascade device, the center frequency of the parallel resonant RLC circuit decreases.

[0057] The second innovative adjustment i nvolves coupling the resonant circuit of the LNA to a switched capacitance circuit. The switched capacitor includes a. switch, whose gate is driven by a clock and where the switch drives a capacitive load. This switched capacitor circuit includes a mixer switch (MOS device) and capacitive load of the differential amplifier. The switched capacitor circuit places a resistance across the resonant circuit and is given by R ^:::: l (Cfe) where C is the capacitive gate load of the differential amplifier and f® is the clock frequenc of the quadrature oscillator. This resistive component can be used to adjust the Q or bandwidth of the parallel resonant RLC circuit of the LNA. [0058] Then, in FIG. 4e, assum ng thai the capacitive array of C* and C5 is removed, the width of the M? device can be adjusted with respect to the Ms device to adjust the center frequenc The resistance of the switched capacitor can be used to adjust the Q or bandwidth of the parallel resonant RLC circuit. These size changes and adjustments are made final using simulation results to cover all process, temperature and voltage variations. After final layout and die fabrication, the operation of this inventive circuit technique has been confirmed by actual measurement.

[0059] The results of decreasing the channel width of M ₇ with a parasitic capacitive load are provided i n Figs. 5a-d. The upper cascode devi ce (M?) in the common source L NA. of FIG. 4e was varied in width while the width of the lower device (Ms) remained constant and the circuit was simulated to determine the NF (Noise Figore) and the Gain of the common source LNA. The dashed and solid lines in all of F!Gs. 5a-d correspond to two different ratios of the width of the upper device (M7) to the width of the lower device (MS) or W^ S. These two ratios have been reduced to a common denominator of 8. The ratio W ? VM80.f the dashed line is 6/8 while that of the solid li e corresponds to a ratio of 5/8.

[0060] FIG. 5a provides the NF at (WCS) Worst Case Slow Case (longer channel lengths, low power supply voltage and high temperature). The dotted line shows a minimum in the NF at about 68GHz while the solid line shifts the minimum towards 63GHz:, Thus, as the upper device is reduced to a ratio of 5/8, the NF is reduced by 0. 16dB at 60GHz when compared to the initial ratio of 6/8. FIG. 5b provides the NF results for the (BCF) Best Case Fast Casef shorter channel lengths, high power supply voltage and low temperature),

[0061 ] FIG. 5c provides the S21 or forward transmission coefficient (forward gain) at WCS. Note that the peak of the solid curve corresponding to a ratio of 5/8 is shifted to the left, decreasing the center frequency. At 60GHz, the forward gain is increased by 3dB. FIG. 5d provides the S21 results for the BCF case. Thus, for the common source LNA of FIG. 4e, assuming that the capacitive array of C4 and C5 is removed,, the ratio of ?/W.MS was set to 5/8. Ideally, to achieve good linearity in the LNA requires that the upper device of the cascode have a width larger than the lower device. The upper device would introduce a smaller voltage drop and increase the available swing of the signal; however, the curves of FIG. Sa-d would then shift to the right, increasing the F and the center carrier frequency outside the desired range. The ldb compression point is monitored to arrive at a design with an acceptable ldb compression point where the NF is reduced, the gain is increased at 60GHz and the bandwidth is shifted to lower frequencies.

[0062] A Gilbert mixer is illustrated in FIG. 6a comprising of the two devices M _g j and M _S2 which are switched by the rf _ist and rf _jM signals, respectively. The drain of device M _g i is coupled to the common node 6-1 of the first mixer switch gated by the in-phase clock (<¾ and its compliment) The drain of device is coupled to the common node 6-2 of the second mixer switch gated b the in-phase clock (©j and its compliment). The outputs of the first mixer switch are combined with the outputs of the second mixer switch as illustrated to generate the ifj ,« _t' signal. A load attached to each of the two outputs couples the Gilbert mixer to a power supply to supply energy to the circuit. The intermediate frequency contains the sum and difference frequency spectrum between the output signal spectrum carried by the rf _in and rf _in and the in-phase clock ((¾ and its compliment). Mote that the energy carried by the output signal spectrum is only applied to the gates of M _g i and hz and this energy does not directly contribute to powering or providing energy to operate the mixer. If this energy could power the mixer, the energy usage of the mixer can potentially be minimized. A similar circuit is used to generate the signal except that the mixer switches axe clocked by the quadrature dock (® _Q and its compliment). A quadrature clock is shifted 90° degrees from the in- phase clock.

[0063] FIG 6b illustrates a block diagram of one embodiment of the invention. A quadrature oscillator generates four equally displaced clock phases: βι, Θ{, OQ and Θο at 0°, 180°, 90° and 270°, respectively The clocks βι and Θ. are the in-phase and inverse in-phase clocks while the ®Q and @ _Q are known as the quadrature and inverse quadrature clocks. The load on each of these dock nodes is identical insuring that the clock output is evenly loaded, thereby preventing any skew between these clock signals from developing. The LN A outputs are applied to common nodes 6-3 and 6-4 of the upper and lower mixer switches. The LNA feeds the amplified signal from a source through the L A to the coupling capacitor _tmii} , The capacitor C _«o« p couples the output signal of the LNA to the common nodes 6-3 and 6-4 of the two mixer switches. Since the upper mixer switch is clocked by the in-phase clocks, only the in-phase current component ¾ is converted into if _lwrt and 18

since the lower mixer switch is clocked by the quadrature-phase clocks, only the quadrature-phase current component JQ is converted into ifqout.

[0064] FIG. 7a depicts the device configuration for the block diagram given in FIG. 6b. The top mixer switch of .FIG. 6b is on the left side of FIG. 7a and comprises MOS devices M ₂ and M¾5 connected to the common node 6-3 while the lower mixer of FIG. 6b is on the right side of FIG. 7a comprises MOS devices and Μ _ί7 connected to the common node 6-4. A voltage divider is formed by resistors « and Ri& and is coupled through a large value resistor Rj ₇ to provide DC biasing for the common nodes 6-3 and 6-4 of the left and right mixer switches and to the common plate electrode of the coupling capacitor C _t -„ _U p.

[0065] The output of the LNA i s coupled to a coupling capacitor C _Wl „ _p , The coupling capacitor applies the average currents Ii and IQ to the common nodes of the left 6-3 and right 6-4 mixer switches, respectively. Note that instead of applying the output signal of the LNA to the gate devices of the Gilbert mixer, for example see M _aJ or M _g2 in FIG. 6a, the signal is instead applied to the common nodes 6-3 and 6-4 of the left and right mixer switches as illustrated in FIG. 7a. Unlike the Gilbert mixer, this embodi ment of mixer switches is dri ven by the average AC current output of the LNA to power the inventive mixer. The miser switch ,\¾5 clocked by the one of the quadrature clocks and the load capacitance of the mixer switch M25 is the gate capacitance of M» which together form a switched capacitor circuit. The switched capacitor presents a load resistive to the resonant circuit of the LNA according to R _L - l/((C _& u ₃ Xfe ) where Rj. is the load resistance placed in parallel to the resonant circuit, C½3 is the capacitance of the load device M& and f® is the frequency of the quadrature clock. This resistance Ri, can be used to de-Q's or increase the bandwidth of the tank circuit in the LNA.

[0066] The signal of interest exists over a given range of frequencies and the information carried by the input signal is embedded within the signal spectrum. The left mixer comprises devices ₂₁ ~Μ ₂₅ and M and resistors RJJ and R«. The mixer switches M25 and MM are enabled and disabled by two of the quadrature clock signals Θι and ®f. A. mixer switch is equivalent to a switched capacitor circuit where the switch is driven by the clock signal to charge and discharge the gate capacitance (M22, M23 of the differential amplifier with remaining components _2l , Rn and R12. The average current charges/discharges the gate capacitance of Μ.κ and M33 whenever the clock signals Θι and Θι enable the mixer switch gates M ₂ s and M2 . The gate capacitance of M ₂₂ and M23 integrate the current Ij to generate a first and a second voltage applied to the differentia! amplifier. The differential amplifier requires two signals: an input signal and a compliment (or inverse) input signal and generaies an output signal and a compliment output signal , in addition, the impedance of the switched capacitance circuit of the mixer is used to de-Q the resonant circuit, thereby achieving a broader bandwidth with acceptable gain. As the resistance of the resonant circuit decreases, the Q decreases and the bandwidth increases. The device M¾ _s and M« from a current mirror controlled by l ! that feeds current into the differential amplifier comprising fcf _2J , ₂₂ , M23, « and _ί2 which amplifies the output of the ¾ signal mixed by ®j and Θι to outputs. The outputs of if teat are extracted just above these two resistors R and R _i2 .

[0067] Similarly, the right mixer comprises devices _2C -M ₃₀ and Μ¾ _β and resistors R _J3 and R ₁₄ . The mixer switches _2f) and M ₂ ?are enabled and disabled by two of the quadrature clock signals Q and 0Q. The current. ½ charges/discharges the gate capacitance ofM _2S and M¾> whenever the clock signals ®Q and ®Q enables the gates M _2I , and M ₂₇ . The device M _K and Μ» from a current mi ror controlled by I i that feeds current into the differential amplifier comprising IV¾s, M. % Mji), i ₃ and M which ampli fies the output of the IQ signal mixed by Q and ¾> to generate the Ί( _Μ ί outputs. The outputs of ii „«t are extracted just above these two resistors 1½ and

[0068] FIG- 7b provides the measured result of the common source L A and the switched capacitor driven mixer. The measured maximum gain of the front end of the WiGig receiver suffices the required specifications. Instead of using the constant parasitic capacitive load in the simulation models for the results provided in FIGS. 5a~d ₃ the measured results provided in FIG. 7b corresponds to the dynamic parasitic capacitive load of the mixer being mixed with the local quadrature oscillators. In particular, note that within the range of allowed bandwidth (57-6 GHz), the gain of the front end remains within 3.2dB of the maximum gain at 63GHz.

[0069] FIG. 8» presents the top die vie of the layout of the common source LNA, the inductors and the mixer . Referring to FiG. 4a, the source of the input signal (in$) arrives at the top on metal 8 layer. The metal 8 layer is patterned into a spiral inductor Li+ At the end of inductor L^ a via connects to a metal 7 layer. The metal 7 layer couples to a via stack and provides the signal to the gate of device M-¾. The drain of device M* is couple through another via stack to the metal 8 layer forming LB The other end of hn is coupled to VSS. Note that there is mutual magnetic coupling between the inductors L and Lis. The peaking inductor Lie formed in the metal 8 layer couples and band pass filters the signal at the drain of M» to the source of M ₇ . The gate of M? is coupled to V D (not shown) while the drain couples to the inductor L _iS formed in the metal 8 layer. The other end of Lis is coupled to a via to the metal 7 layer and connects to VDD. The drain of M-? is also coupled to one plate of the coupling capacitor C _c . _m p formed in the metal 8 layer. Beneath this metal 8 layer is a metal 7 layer forming the lower plate of the coupling capacitor€«,„ρ and the lower plate is coupled to the two mixers as shown in FIG. 7a. The view along the cut A-A* is presented in FIG. 8b. The top metal 8 layer forms one plate of the capacitor and is separated by oxide from the lower metal 7 layer forming the other plate of the capacitor C _misp .

[0070] FIG. 8c illustrates a cross-sectional view of a via stack within a die with eight metal layers.

A via stack also known as a stacked via, stacked plug, or stacked contact is illustrated in FIG-. 8c. The via between different metal layers are placed over the via of the lower layers to save on area. However, as one progresses from poly to metal I to metal 2 and up to metal 8, the vias, for example 8-1 and 8-3, increase in diameter. Each via, for instance, the via 8-1 and the metal 1 layer 8-2 introduce contact resistance and inductance. The via 8-3 and metal 5 layer 8-4 also introduce contact resistance and resistance into the path. The via stack can be tapped to ntroduce/extract a signal into/out of the stack or alter the parasitics in a circuit. The tapping occurs when a metai layer is extended from the stack and this location is called a tap point. Typically, the top metals in a technology are significantly thicker than any of the lower layer metals. The dielectric layers surround the vias and the metal segments M ₂ , ^' Mj, etc. and each one of these dielectric layers is approximately 0.5 μηι thick. The metal I through metal 7 layers are also about 0.5 μηι thick while the metal 8 layer can be over 1 pm thick. The height of these via stacks is about 3 to 4 pm.

[0071] Finally, i t is understood that the above description are only illustrati ve of the pri nciple of the current invention. Various alterations, improvements, and modifications will occur and are intended to be suggested hereby, and are within the sprit and scope of the invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. .Rather, these embodiments are provided so that the disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the arts, ft is understood that the various embodiments of the invention, although different, are not mutually exclusive. In accordance with these principles, those skilled in the art may devise numerous modifications without departing from the spirit and scope of the invention. Although the circuits were described using CMOS, the same circuit techniques can be applied to depletion mode devices and BIT or biploar circuits, since this tecnologv allows the formation of current sources and source folloowers. When a device is specified, the device can be a transistor such as an N-MOS or P-MOS. The CMOS or SOI (Silicon on Insulator) technology provides two enhancement mode channel types: N-MOS (it-channel) and P-MOS (p-channel) devices or transistors. The via stacks can be fabricated using tungsten or copper. In addition, a network and a portable system can exchange information wirelessly by using communication techniques such as TJDMA (Time Division

Multiple Access), FDMA (Frequency Division Multiple Access), CDMA (Code Division Multiple Access), OFDM (Orthogonal Frequency Division Multiplexing ), IJWB (Ultra Wide Band), WiFt, WiGig, Bluetooth, etc. The network can comprise the phone network, IP (Internet protocol) network, LAN (Local Area Network), ad hoc networks, local routers and even other portable s stems.