Title:
INSPECTION CHIP
Document Type and Number:
WIPO Patent Application WO/2014/061636
Kind Code:
A1
Abstract:
Provided is an inspection chip that improves quantification precision. In the inspection chip (2), a virtual plane (H1) that is parallel to a quantitative surface (T) forms an angle (A) with a sample supply unit wall surface (119). A virtual plane (H2) that is parallel to the quantitative surface (T) forms an angle (B) with a first passage wall surface (120). A virtual plane (H3) that is parallel to the quantitative surface (T) forms an angle (C) with a second passage wall surface (122). A virtual plane (H4) that is parallel to the quantitative surface (T) forms an angle (D) with a holding section wall surface (118). The inspection chip (2) is configured so as to satisfy the following relationships: Angle (A) < Angle (B) < Angle (C); Angle (A) < Angle (D); Angle (D) < Angle (B). By satisfying these relationships, it is possible to accurately perform quantification without causing a shortage of a sample when quantifying said sample using a sample quantification unit (114).
Inventors:
OSHIKA YUMIKO (JP)
YOSHIMURA CHISATO (JP)
YOSHIMURA CHISATO (JP)
Application Number:
PCT/JP2013/077911
Publication Date:
April 24, 2014
Filing Date:
October 15, 2013
Export Citation:
Assignee:
BROTHER IND LTD (JP)
International Classes:
G01N35/00
Foreign References:
| JP2012078115A | 2012-04-19 | |||
| JP2011237325A | 2011-11-24 | |||
| JP2011214884A | 2011-10-27 |
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