Title:
INSTRUCTION PROCESSING METHOD AND INSTRUCTION PROCESSING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2022/123722
Kind Code:
A1
Abstract:
This instruction processing method is executed by an instruction processing circuit that reads, from a memory, an instruction stored in a buffer memory, on the basis of a read instruction. The method comprises: steps (S105, S106) for storing an instruction and an identifier for identifying the instruction in the buffer memory, wherein the identifier includes an error detection and correction code for detecting and correcting an error of the identifier; steps (S109, S111) for reading, on the basis of the read instruction, a part of the identifier and the instruction or only the identifier from the buffer memory, and performing error detection of the identifier on the basis of the error detection correction code included in the read identifier; and steps (steps S112 to S114) for, when there is a correctable error in the error detection result, outputting the corrected identifier together with the instruction, and when there is an uncorrectable error in the error detection result, discarding without outputting the instruction. This makes it possible to effectively suppress the adverse effects of soft errors on a small circuit scale.
Inventors:
ITO TSUYOSHI (JP)
TANAKA KENJI (JP)
ARIKAWA YUKI (JP)
TERADA KAZUHIKO (JP)
TAKEYA TSUTOMU (JP)
SAKAMOTO TAKESHI (JP)
TANAKA KENJI (JP)
ARIKAWA YUKI (JP)
TERADA KAZUHIKO (JP)
TAKEYA TSUTOMU (JP)
SAKAMOTO TAKESHI (JP)
Application Number:
PCT/JP2020/046028
Publication Date:
June 16, 2022
Filing Date:
December 10, 2020
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE (JP)
International Classes:
G06F11/10
Foreign References:
| JP2011209905A | 2011-10-20 | |||
| JP2009301462A | 2009-12-24 | |||
| JP2020532780A | 2020-11-12 |
Attorney, Agent or Firm:
YAMAKAWA, Shigeki et al. (JP)
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