INTEGRATED CAMERA MODULE AND METHOD OF MAKING SAME RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 61/870,084, filed August 26, 2013, and which is incorporated herein by reference.

FIELD OF THE INVENTION

[0002] The present invention relates to camera modules used on mobile devices such as cell phones.

BACKGROUND OF THE INVENTION

[0003] The present invention relates to the method of compaction for a mobile camera system by reducing its overall size. More specifically, abundance of real estate can be gained by improving the outdated LED packaging technology used in conjunction with mobile camera devices.

[0004] Over the years, a great deal of research and work has been made into reducing the size of image sensor die and its packaging size. Using advanced wafer level technology, manufacturers can now achieve chip scale package, which means the complete package's real estate area is no larger than the die itself.

[0005] Meanwhile, the LED (light emitting diode) unit used as a flash source for the camera unit (and commonly used as a flashlight in a flashlight mode) is still using very primitive packing technology that was outdated long ago, and it has no place in today's mobile devices. Typically, the LED unit is a separate component from the camera unit, and is connected thereto using a flex PCB or other connector. Not only does this configuration use excessive space, but it requires a separate mounting structure to secure these two separate components adjacent each other so that they can then be electrically connected to each other.

[0006] There is a need for a compact solution for both the camera unit and the LED unit used as a light source for the camera unit.

BRIEF SUMMARY OF THE INVENTION

[0007] The aforementioned problems and needs are addressed by a camera module that includes a substrate of conductive silicon having top and bottom surfaces, a sensor device and an LED device. The substrate includes a first cavity formed into the bottom surface of the substrate and having an upper surface, an aperture extending from the first cavity upper surface

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375046-995460 1 Atty Dckt No.: 375046-995460 PATENT to the top surface of the substrate, and a second cavity formed into the top surface of the substrate and having a lower surface. The sensor device includes at least one photodetector, is disposed at least partially in the first cavity, and is mounted to the first cavity upper surface. The LED device includes at least one light emitting diode, is disposed at least partially in the second cavity, and is mounted to the second cavity lower surface.

[0008] A method of forming a camera module includes providing a substrate of conductive silicon having top and bottom surfaces, forming a first cavity into the bottom surface of the substrate, the first cavity having an upper surface, forming an aperture extending from the first cavity upper surface to the top surface of the substrate, forming a second cavity into the top surface of the substrate, the second cavity having a lower surface, mounting a sensor device to the first cavity upper surface wherein the sensor device includes at least one photodetector, and mounting an LED device to the second cavity lower surface, wherein the LED device includes at least one light emitting diode.

[0009] Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figs. 1-13 are side cross sectional views of a substrate handler showing the sequential steps in forming the camera module of the present invention.

[0011] Figs. 14A-14C are side cross sectional views showing various configurations of the senor package.

[0012] Figs. 15A-15H are side cross sectional views showing varying embodiments of the camera module of the present invention.

[0013] Fig. 16 is a flow chart illustrating the steps for processing and combining different images (one low resolution, one high resolution) from two image sensors to form a higher quality final image.

[0014] Fig. 17 is a flow chart illustrates the steps for processing and combining different images from two image sensors to form a three dimensional final image.

DETAILED DESCRIPTION OF THE INVENTION

[0015] The present invention is a camera module size reduction solution. By using wafer level technology on the LED unit and also merging the LED unit and the image sensor die onto

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375046-995460 2 Atty Dckt No.: 375046-995460 PATENT a single handler, greater space savings and electrical connectivity, and closer proximity and alignment between the image sensor and LED unit, can be achieved.

[0016] The formation of the camera module 1 begins with a conductive silicon substrate (wafer) 10, also referred to as the handler. This substrate 10 will be shaped into a host substrate for the LED die and the image sensor die. A layer of photoresist 12 is deposited on the silicon substrate 10 (at least on the top and bottom surfaces). The photoresist deposition method can be spray coating or any another appropriate deposition method(s). The photoresist 12 is exposed and etched using appropriate photolithography processes that are well known in the art to selectively remove just a portion of the photoresist 12, leaving exposed a selected portion of the bottom surface of the substrate 10. An anisotropic dry etch is applied to the exposed portion of the silicon substrate to form a first cavity 14 into the bottom surface of the silicon substrate 10, resulting in the structure in Fig. 1. The enchant can be CF4, SF6, NF3, C12, CC12F2 or any other appropriate etchant. The first cavity can have slanted/tapered side walls, or vertical side walls as shown in 1.

[0017] After the photo resist 12 is removed (e.g. by using sulfuric acid, acetone or any other photoresist stripping method that are well known in the art), another layer of photo resist 16 is deposited on the silicon substrate 10 (at least on the top and bottom surfaces, including the surfaces inside the first cavity 14). The photoresist deposition method can be spray coating or any another appropriate deposition method(s). The photoresist 16 is exposed and etched using appropriate photolithography processes that are well known in the art to selectively remove portions of photoresist 16, leaving exposed a portion of the top surface of the substrate 10 that is over first cavity 14, and a corresponding portion of the top surface of first cavity 14. An anisotropic dry etch is applied to the exposed portions of silicon substrate 10 to form an aperture 18 that extends through the substrate 10 (from the cavity top surface to the substrate top surface), as illustrated in Fig. 2. The Enchant can be CF4, SF6, NF3, C12, CC12F2 or any other appropriate etchant. Preferably, the lateral dimensions of aperture 18 are smaller than the lateral dimensions of first cavity 14, leaving shoulders 20 of substrate 10 at the boundary of first cavity 14 and aperture 18 (i.e. a portion of the upper surface of first cavity 14 forms shoulder 20).

[0018] After photoresist 16 is removed, another layer of photoresist 22 is deposited on the silicon substrate 10 (at least on the top and bottom substrate surfaces, inside the first cavityl4, and the inside the aperture 18). The photoresist 22 is exposed and etched using appropriate photolithography processes that are well known in the art to selectively remove a portion of

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375046-995460 3 Atty Dckt No.: 375046-995460 PATENT photoresist 22, leaving exposed a portion of the bottom surface of substrate 10. An anisotropic dry etch is applied to the exposed portion of silicon substrate 10, leaving a second cavity 24 formed into the bottom surface of the substrate 10, as illustrated in Fig. 3. The second cavity 24 can have slanted/tapered side walls, or vertical side walls as shown in 3.

[0019] After photoresist 22 is removed, another layer of photoresist 26 is deposited on the silicon substrate 10 (at least on the top and bottom substrate surfaces, inside the first and second cavities 14 and 24, and the inside the aperture 18). The photoresist 26 is exposed and etched using appropriate photolithography processes that are well known in the art to selectively remove a portion of photoresist 26, leaving exposed a portion of the top surface of substrate 10 (opposite the second cavity 24). An anisotropic dry etch is applied to the exposed portion of silicon substrate 10, leaving a third cavity 28 formed into the top surface of the substrate 10, as illustrated in Fig. 4. The third cavity 28 can have vertical side walls, or slanted/tapered side walls as shown in 4.

[0020] After photoresist 26 is removed, another layer of photoresist 30 is deposited on the silicon substrate 10 (at least on the top and bottom substrate surfaces, inside cavities 14, 24, 28 and the inside the aperture 18). The photoresist 30 is exposed and etched using appropriate photolithography processes that are well known in the art to selectively remove a portion of photoresist 26, leaving exposed a portion of the bottom surface of third cavity 28. An anisotropic dry etch is applied to the exposed portion of silicon substrate 10, which extends downwardly the third cavity 28 until it meets the second cavity 24 (resulting in a second shoulder 34 where the second and third cavities 24, 28 meet - i.e. a portion of the lower surface of the third cavity 28 forms shoulder 34), as shown in Fig. 5.

[0021] After photoresist 30 is removed, a plurality of VIA holes 36 are next formed that extend through the substrate 10 (i.e. extend from the top surface to the bottom surface of the substrate 10). The VIA holes 36 can be made by laser, dry etch, wet etch or any another appropriate VIA hole forming method(s) that are well known in the art. Preferably, a dry plasma etch is used to form the VIA holes 36. The VIA holes 36 can have tapered sidewalls (i.e. funnel shaped holes ), or vertical sidewalls as shown in Fig. 6. The number and positions of the VIA holes 36 can vary depending on the layout of the module, and are not limited to the four exemplary VIA holes 36 illustrated in Fig. 6.

[0022] A layer of dielectric material 38 is formed on the various surfaces of the silicon substrate 10 (including in holes 36 and in cavities 14, 24, 28). For example, dielectric layer 38

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375046-995460 4 Atty Dckt No.: 375046-995460 PATENT can be a spray coated polymer, or any other appropriate dielectric material (e.g. silicon oxide, silicon nitride, etc.). A layer of electrically conductive material 40 is formed over the dielectric layer 38. The electrically conductive layer 40 can be copper, aluminum, conductive polymer and/or any other appropriate electrically conductive material(s). The electrically conductive layer can be deposited by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), plating or any other appropriate deposition method(s). Preferably, the electrically conductive layer 40 is a first layer of titanium and a second layer of aluminum, both deposited by Physical Vapor Deposition (PVD). The VIA holes 36 are either coated with the electrically conductive material 40, or completely filled with the electrically conductive material 40 as shown in Fig. 7, to form electrically conductive leads extending through the substrate 10.

Optionally, angled sidewall reflector portions 28a of third cavity 28 can have their reflective index increased by the deposition of an additional layer of silver or any other appropriate reflective material on that portion of the electrically conductive layer 40.

[0023] A layer of photoresist 42 is deposited on the conductive layer 40. Photoresist is exposed and etched using appropriate photolithography processes that are well known in the art to selectively remove the photoresist 42, leaving portions of the conductive material exposed. Using dry or wet etching methods, exposed portions of the conductive material 40 are removed. The remaining portions of the conductive material 40 constitute conductive leads 44 (including the conductive material 40 in the VIA holes 36 and in the first cavity 14), and the reflector portions 28a (in the third cavity 28). Preferably, appropriate wet etching chemicals are used for this etching step. The resulting structure is shown in Fig. 8.

[0024] After photoresist 42 is removed, an encapsulant layer 46 of insulation material is deposited on the bottom side of the silicon substrate 10, including over the conductive leads 44. Encapsulant layer 46 can be polyimide, ceramics, polymer, polymer composite, metallic oxide, silicon dioxide, epoxy, silicone, porcelain, nitrides, glass, ionic crystals, resin, or a combination of aforementioned materials or any other appropriate dielectric material(s).

Encapsulant layer 46 is preferably 1 to 3 μιη in thickness, and the preferred material is liquid photolithography polymer such as solder mask which can be deposited by spray coating. If the VIA holes 36 are coated but not filled with the conductive material 40, then optionally, the VIA holes 36 can be filled by the encapsulation material 46. Portions of the encapsulation layer 46 are selectively removed (e.g. using well known lithography process(es)), to expose selected portions of the underlying conductive layer 40, which constitute contact pads 48 and

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375046-995460 5 Atty Dckt No.: 375046-995460 PATENT the rerouted contact pads 50. There are also contact pads 48 on the top surface of the substrate as well, and a reflector portion . The resulting structure is shown in Fig. 9.

[0025] An LED device (e.g. die) 56 is picked and placed onto the shoulder 34 between the second and third cavities 24, 28, and glued into place. The LED die 56 includes one or more light emitting diodes 58 formed on or in a substrate 60 and electrically connected to bond pads 62 on the die substrate 60. LED die 56 is well known in the art, and therefore not further described herein. A sensor device (e.g. CMOS sensor package) 64 is mounted onto shoulder 20 in the first cavity 14, for example, by electrical connectors (e.g. ball grid connectors) between the contact pads of each. CMOS sensor package 64 includes a plurality of photo detectors formed on or in a substrate 68 and electrically connected to contact pads 70 on the substrate 68. CMOS sensor package 64 is well known in the art, and therefore not further described herein. An optional power capacitor 60 can be mounted by a standard pick and place SMT technique to one of the contact pads 48. An optional heat sink 74 can be mounted to the back side of the LED die 56 and within the handler's second cavity 24. The resulting structure is illustrated in Fig. 10.

[0026] A conventional wirebonding technique can be used to connect the LED bond pads 62, to the contact pads 48 over or connected to the conductive material 40 in the VIA holes 36, with bonding wires 76. A lens/encapsulant 78 is then deposited over the LED die 56 and its wirebonds 76, which protects the wirebonding 76 and also acts as a lens for the light emitted from the LEDs 58, as illustrated in Fig.11. The lens/encapsulant can be made of acrylic plastic, epoxy or any other appropriate materials. Alternatively, the lens/encapsulant can be made as a curved member 80 of pre-molded glass, plastic or any other appropriate lens worthy material. The curved member 80 is hermetically sealed and forms a cavity 82 containing and protecting the LED die 56 and its wirebonding 76, as illustrated in Fig. 12. The cavity 82 can be filled with any appropriate gas, liquid or even be evacuated (i.e. a vacuum).

[0027] Interconnects 84, such as ball grid array (BGA), land grid array (LGA), bumping, copper pillar or any other appropriate interconnects are formed on and in electrical connection with the contact pads 48, 50 on the bottom surface of the substrate 10. Ball grid array is one of the preferred methods of interconnection and it can be deposited by screen printing followed by a reflow process. An optional lens or lens module of choice is bonded on to substrate 10 and disposed over the active area of the image sensor 64, thus encapsulating the side of sensor 64 containing the photodetectors 66. Preferably, a lens module 86, having a housing 88 in

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375046-995460 6 Atty Dckt No.: 375046-995460 PATENT which lenses 90 are secured, is mounted to the upper surface of substrate 10 and over aperture 18. The final structure of camera module 1 is shown in Fig. 13.

[0028] The camera module 1 is a compact, integrated packaging of both the image sensor package 64 and the LED light source 56. The substrate 10 provides locations on which to securely mount the image sensor 64 and LED light source 56, and provides electrical connectivity for both devices, with all electrical contacts for both devices 56, 64 on the bottom surface of the substrate 10. Handler 10 not only provides electrical connections for image sensor package 64 and LED light source 56, but provides mechanical protection for these devices as well, as both devices are recessed between the top and bottom surfaces of handler 10 (although the relative heights of these components can be different).

[0029] Figures 14A-14C illustrate various embodiments of the image sensor 64. As shown in Fig. 14 A, a protective substrate 92 can be mounted over the photodetectors 66 using a spacer material 94. Leads 96 with rerouted contact pads 98 can be formed on the upper surface of substrate 68. The image sensor in Fig. 14A is shown as the image sensor 64 used for camera module 1 in Figs. 10-13. As shown in Fig. 14B, the leads 96 (electrically connected to contact pads 70) and rerouted contact pads 98 can be formed down into a trench or recess formed into the top surface of substrate 68. As shown in Fig. 14C, the protective substrate 92 can be formed without a center aperture (as shown in the other embodiments) to seal the active area of the sensor. Additional, electrical contacts 100 (electrically connected to contact pads 70) can be formed through the spacer material 94.

[0030] Figures 15A-15H illustrate alternate embodiments of the camera module 1.

Specifically, Figure 15A shows the camera module 1 with the image sensor 64 of Fig. 14B. Figure 15B shows the camera module 1 with the image sensor 64 of Fig. 14C. Fig. 15C shows the use of vertical side walls 102 for the third cavity 28. Fig. 15D shows the inclusion of a logic chip 104 mounted under the LED die 56 (in second cavity 24) and to electrical leads 106. Fig. 15E shows a heat sink 108 mounted to the logic chip 104 of Fig. 15D. Fig. 15F shows the inclusion of a power capacitor 110 mounted under the LED die 56 (in second cavity 24) and to electrical leads 106. Fig. 15G shows the inclusion of a power capacitor 110 mounted to the top surface of substrate 10, with its electrical connection rerouted through an electrical connector 114 in a via hole to the bottom surface of the substrate 10.

[0031] Fig. 15H shows the LED die 56 disposed between two CMOS sensor packages 64 on the same substrate 10. The two CMOS sensors 64 could have one or more different optical

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375046-995460 7 Atty Dckt No.: 375046-995460 PATENT sensing characteristics (e.g. different imaging resolutions (such as different pixel numbers, different pixel sizes, different active area sizes, and/or lens modules 86 of different lens focusing characteristic(s), etc.), different spectral properties (such as varying sensitivities to different wavelengths or wavelength ranges), etc., whereby together the two optical sensors provide greater imaging capabilities than just a single image sensor. For example, the two optical sensors can be used to provide higher single image quality, or could be used to create three dimensional images. Fig. 16 illustrates one exemplary technique for processing and combining different images (one low resolution, one high resolution) from two image sensors to form a higher quality final image. Fig. 17 illustrates another exemplary technique for processing and combining different images from two image sensors to form a three dimensional final image.

[0032] It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein, but encompasses any and all variations falling within the scope of the appended claims. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method steps need be performed in the exact order illustrated or claimed, but rather in any order that allows the proper formation of the camera module of the present invention. Lastly, single layers of material could be formed as multiple layers of such or similar materials, and vice versa.

[0033] It should be noted that, as used herein, the terms "over" and "on" both inclusively include "directly on" (no intermediate materials, elements or space disposed therebetween) and "indirectly on" (intermediate materials, elements or space disposed therebetween). Likewise, the term "adjacent" includes "directly adjacent" (no intermediate materials, elements or space disposed therebetween) and "indirectly adjacent" (intermediate materials, elements or space disposed there between), "mounted to" includes "directly mounted to" (no intermediate materials, elements or space disposed there between) and "indirectly mounted to" (intermediate materials, elements or spaced disposed there between), and "electrically coupled" includes "directly electrically coupled to" (no intermediate materials or elements there between that electrically connect the elements together) and "indirectly electrically coupled to"

(intermediate materials or elements there between that electrically connect the elements together). For example, forming an element "over a substrate" or "on a substrate" can include

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375046-995460 8 Atty Dckt No.: 375046-995460 PATENT forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements therebetween.

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