Title:
INTEGRATED CIRCUIT BOARD EMULATION MULTI-LEVEL DISTRIBUTED PARALLEL COMPUTING METHOD
Document Type and Number:
WIPO Patent Application WO/2023/036144
Kind Code:
A1
Abstract:
Provided in the present invention is an integrated circuit board simulation multi-stage distributed parallel computing method, belonging to the technical field of integrated circuit simulation. The method of the present invention comprises the following steps: S100, calculating the number of nodes; S200, allocating tasks; S300, calculating and solving; and S400, judging convergence. In the present invention, by means of dynamic multi-machine parallel, computing resources can be utilized to the maximum extent, the simulation efficiency is improved, and finally achieving the purpose of shortening the design cycle. Moreover, in the simulation process, using a dynamic result analysis method can accurately determine a frequency point that needs to be solved, and an accurate full-band result can be completed with a minimum number of solutions.
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Inventors:
DAI WENLIANG (CN)
JIANG LIGUO (CN)
LING FENG (CN)
ZHANG JIAN (CN)
JIANG LIGUO (CN)
LING FENG (CN)
ZHANG JIAN (CN)
Application Number:
PCT/CN2022/117348
Publication Date:
March 16, 2023
Filing Date:
September 06, 2022
Export Citation:
Assignee:
XPEEDIC CO LTD (CN)
International Classes:
G06F30/33; G06F9/50
Foreign References:
| CN113722966A | 2021-11-30 | |||
| CN111898330A | 2020-11-06 | |||
| CN107247686A | 2017-10-13 | |||
| CN103186689A | 2013-07-03 | |||
| US20180217873A1 | 2018-08-02 |
Attorney, Agent or Firm:
SHANGHAI LEHONG PATENT AGENCY (GENERAL PARTNERSHIP) (CN)
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