Title:
INTEGRATED CIRCUIT HAVING FREQUENCY DIVIDER CIRCUIT ADAPTABLE FOR HIGH-SPEED TESTING
Document Type and Number:
WIPO Patent Application WO/1980/002880
Kind Code:
A1
Abstract:
An integrated circuit having a frequency divider circuit adaptable for high-speed testing. The frequency divider circuit is split into two stages of a pre-stage frequency divider circuit (12) and a post-stage frequency divider circuit (14). An output buffer circuit (3) and a testing signal-input circuit (4) are connected in parallel to an alarm terminal (7). The testing signal applied to the alarm terminal (7) is fed to the poststage frequency divider circuit (14) through the testing signal-input circuit (4) and a switching circuit (13).
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Inventors:
MONMA H (JP)
ISHIGURO M (JP)
TAKAHASHI M (JP)
ISHIGURO M (JP)
TAKAHASHI M (JP)
Application Number:
PCT/JP1980/000138
Publication Date:
December 24, 1980
Filing Date:
June 19, 1980
Export Citation:
Assignee:
FUJITSU LTD (JP)
MONMA H (JP)
ISHIGURO M (JP)
TAKAHASHI M (JP)
MONMA H (JP)
ISHIGURO M (JP)
TAKAHASHI M (JP)
International Classes:
H03K21/40; G04D7/12; G04G99/00; (IPC1-7): G04C3/00; G01R31/26; G04C21/00; G04D7/00; G04G1/00; H03K21/34
Foreign References:
| JPS52122161A | 1977-10-14 | |||
| JPS5570777A | 1980-05-28 | |||
| JPS552949A | 1980-01-10 |
Other References:
YOKOI YOJIRO "Microcomputer Kiso Gijutsu Manual" The first impression of the sixth adition (1977-12-5) Page 124, Fig. 7.2.
See also references of EP 0030564A4
See also references of EP 0030564A4
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