Integrated circuit inductor with small floating metal structures

The present invention relates to an integrated circuit inductor structure and is more particularly directed to an integrated circuit inductor containing large amounts of small floating metal structures with a low impact on the inductor performance over a large frequency range. On-chip spiral inductors, despite their excessive area consumption and

moderate quality factor (Q = , where ω is the operating frequency in radians per second

R for the inductor, L is the inductance of the inductor, and R is the resistance of the inductor), play an essential role in front-end radio frequency (RF) circuits, such as voltage-controlled oscillators (VCOs), low-noise amplifiers (LNAs) and impedance matching networks for example, while realizing narrow-band impedance matching, filter and decoupling functionality.

In modern advanced integrated circuit (IC) processes, such as 90 nm and beyond node complementary metal oxide semiconductor (CMOS) processes, design rules, like chemical mechanical polishing or planarization (CMP) density rules, require inclusion of considerable amounts of floating dummy metal fill patterns inside and in the vicinity of the inductor tracks, in order to guaranty better circuit manufacturability and yield.

Nevertheless, these dummy structures are source of Eddy currents induced by the passage of the magnetic field of the inductor into them, which leads to higher resistive losses of the inductor and thus to a deterioration of the quality factor Q. Furthermore, at increasing high frequencies, a floating dummy metal fill pattern has a dielectric constant ε approaching infinity and a magnetic permeability μ approaching zero, which results in enhancement of parasitic capacitance and reduction of the

inductance, respectively, i.e., in a degradation of the resonant frequency f _res (= τ= iπ^LC

Hertz) and the quality factor Q, respectively.

It is therefore an object of the present invention to provide a high performance integrated circuit inductor structure containing large amounts of small floating metal structures as required by the metal density rules in advanced silicon technologies, which do not degrade the inductor performance over a large frequency range, as well as an associated method for providing such a high performance integrated circuit inductor structure.

This object is achieved by an integrated circuit inductor structure as claimed in claim 1 and a method as claimed in claim 14.

The semiconductor device according to the invention comprises at least: a) a substrate comprising a semiconductor material; b) an inductive element, said inductive element being disposed upon said substrate and comprising at least one conductive line generating an electromagnetic field around itself when passed through by a current; c) a floating metal structure; wherein, - said floating metal structure is disposed within a predetermined distance away from said inductive element; said floating metal structure has a predetermined size depending on an operating frequency of said inductive element.

In a first aspect, an integrated circuit inductor structure comprises a substrate made of a material exhibiting a finite conductivity such as a semiconductor, a floating metal structure for meeting the metal density rules in advanced silicon technologies, and an inductive element through which a current may flow to generate an electromagnetic field around it and to induce an Eddy or mirror current in any metal or finite resistivity structure intersected by this field. The floating metal structure is disposed within a predetermined distance away from the inductive element in order to avoid a reduction of the resonant frequency of the inductive element. This distance may optimally correspond to at least three times a distance to the patterned ground shield away from the inductive element.

Moreover, the floating metal structure has a predetermined size depending on the operating frequency of the inductive element. This size shall be chosen as inversely proportional to the operating frequency of the inductive element in order to minimize the Eddy current losses through the floating metal structure and to thereby improve the quality factor of the integrated circuit inductor structure.

Additionally, the integrated circuit inductor structure may comprise a patterned ground shield in order to shield the inductive element from the substrate layer and to thus improve the quality factor of the integrated circuit inductor structure.

The patterned ground shield may consist of a plurality of elongate elements oriented perpendicular to a symmetry axis of the inductive element for inhibiting the flow of Eddy currents, and made of polysilicon or a combination of polysilicon and metal while meeting the poly and metal density rules in advanced silicon technologies.

Furthermore, each elongate element has a predetermined dimension depending on the operating frequency of the inductive element. Thus, the width shall be chosen as inversely proportional to the operating frequency of the inductive element in order to minimize the Eddy current losses through the shield finger and to thereby improve the quality factor of the integrated circuit inductor structure.

The substrate is made of a semiconductor material whose the resistivity will be chosen high in order to minimize the Eddy current losses through it and to thereby improve the quality factor of the integrated circuit inductor structure.

The inductive element can have different geometric patterns and may include a planar or non-planar single-turn inductive element or a planar or non-planar spiral inductive element comprising a plurality of turns.

In a second aspect, a method allows to provide a high performance integrated circuit inductor structure containing large amounts of small floating metal structures, in order to inhibit a decrease of the resonant frequency and to improve the quality factor. The method for providing a high performance integrated circuit inductor structure according to the invention comprises at least a substrate and an inductive element, said method comprising at least the following steps of: a) selecting a patterned ground shield made of a plurality of elongate elements; b) disposing each one of said elongate elements perpendicular to a symmetry axis of said inductive element; c) selecting a width of each one of said elongate elements with respect to an operating frequency of said inductive element; d) selecting a size of a floating metal structure with respect to said operating frequency of said inductive element; e) disposing a floating metal structure within a predetermined distance away from an inductive element of said inductor structure.

Further advantageous developments are defined in the dependent claims.

The present invention will be now described based on preferred embodiments with reference to the accompanying drawings in which: Fig. 1 shows a conventional on-chip single loop inductor with high amounts of dummy metal fill patterns and a center tap;

Fig. 2 shows two conventional ways to connect in series nested inductor loops, in the case of a single spiral (a) and a symmetrical layout (b);

Fig. 3 shows an equivalent circuit model of an integrated symmetrical inductor with center tap, patterned ground shield and dummy metal fill patterns;

Fig. 4 shows the modeling of the impact of a dissipative Eddy current loop L2/R2 on an inductor L to first order by a parallel conductance G;

Fig. 5 shows the Eddy current loops assumed in a rectangular dummy metal fill pattern, wherein r = (xd)/2 and w = (d/2).dx with 0 < x < 1; Fig. 6a shows the measured (Meas) peak quality factor versus simulated (Sim) peak quality factor (Q), for both single-ended (S. E.) and differential (Dif.) quality factor (Q);

Fig. 6b shows the measured (symbols) and simulated (lines) differential quality factor (Q) for four (4) types of single turn 0.5 nH inductors versus frequency (F);

Fig. 7a shows the AC resistance increase versus frequency seen when a metal 1 shield is added to inductors with a polysilicon shield;

Fig. 7b shows the AC resistance increase versus frequency seen when 3 μm dummy metal fill patterns are inserted up to 10 μm from the inner inductor loops;

Fig. 8 shows improvements in differential quality factor of the 0.5 nH inductor simulated for various layout and process modifications (curves No. 1 to 5); Table I gives the outer and inner diameters (D ₀ and D ₁ ), the number of turns

(N), the loop width and space (W and S), the inductance (L) and the inductance error (δL) of the octagonal inductors;

Table II gives the sheet resistances and metal densities used for evaluating the losses of the inductors under consideration; Table III gives the breakdown of the inductor losses (in %) calculated using the predictive inductor model at the frequency f where the peak differential quality factor is obtained.

In the following, a first preferred embodiment of the invention will be described in connection with an integrated spiral symmetric inductor with a center tap such as represented in Fig. 1.

Referring to Fig. 1 and in accordance with the first preferred embodiment, a single loop inductor comprises an inductive element provided on a substrate and having, inside and in the vicinity of the inductor tracks, high amounts of dummy metal fill patterns, as required in order to meet the metal density rules in advanced integrated circuit processes.

Based on design considerations, higher inductance values L of the inductor can be obtained either by increasing the inductor size or connecting in series several inductor loops. Within a given outer and inner diameter and an available metal stack thickness, both the inductance L and the series resistance R _s increase quadratically with the number N of turns, such that the quality factor Q remains roughly the same at a given frequency. Since Q increases with the frequency until about the half of the resonant frequency f _res of the inductor and the resonant frequency f _res rapidly decreases when the number N of turns increases, the peak values of Q for the same footprint diminish for larger inductance values L.

Moreover, a higher resonant frequency f _res can be achieved when the capacitance C among the different inductor loops can be minimized, and nested inductor loops seem to be preferable over stacked inductor loops according to C-C Tang et al. in "Miniature 3-D inductors in standard CMOS process", IEEE J. Solid-State Circuits, vol. 37, No. 4, pp. 471-480, April 2002. These nested inductor loops can be series connected in different ways as depicted in Fig. 2. In Fig. 2a, a single spiral provides the highest resonant frequency since it minimizes the energy stored in the capacitances between adjacent inductor windings, but for many bulk CMOS or BiCMOS applications, a symmetrical layout, as shown in Fig. 2b, suitable to enhance Q through differential excitation is however preferred. When integrated in such a bulk (Bi)CMOS process, the spiral inductor is only a few micron away from the conductive substrate, such as a silicon substrate, and for typical substrate resistivities of 10 ω.cm and higher, Eddy current losses are small.

On the other hand, losses which result of the capacitive coupling between the inductor and the substrate can be eliminated using a proper patterned ground shield (PGS), such as a PGS made of connected polysilicon bars perpendicular to the symmetry axis of the inductor. It slightly reduces the resonant frequency f _res but further improves the peak quality factor Q _max , in particular for single loop inductors, because the effective resistance R _s h of the PGS is much less than the substrate resistance R _su b. Therefore, the PGS short-circuits the substrate resistance R _sh .

In modern CMOS processes, design rules require the inclusion of dummy metal fill patterns inside and in the vicinity of the inductor loops in order to meet certain minimum metal density levels. A reduction of the inductor resonant frequency f _res is avoided when these dummy metal fill patterns are placed as far as possible from the inductor loops, for example at three times the distance to the ground shield away from the inductor loops. This may require some stretching of the process design rules, but since minimum rule features are not required for the inductor loops, this can usually be tolerated. However, inductive effects have a reach longer than capacitive effects, and Eddy current losses in these dummy metal fill patterns are to be considered when optimizing inductor performance. In order to evaluate the impact of these dummy metal fill patterns on the resonant frequency f _res and the quality factor Q, we start from an inductor model based on the equivalent circuit model for a symmetrical inductor such as described by L. F. Tiemeijer et al. in "Predictive spiral inductor compact model for frequency and time domain", Proceedings of International Electron Device Meeting, 2003, pp. 875-878. The model, as depicted in Fig. 3, to which our invention refers, concerns a physics-based wide-band predictive compact model for symmetrical inductors with high amounts of dummy metal fill patterns which additionally takes into consideration the Eddy current losses in the substrate, the patterned ground shield and the dummy metal fill patterns.

In this 5 -terminal model using a fourth order L/R network, R and L represent the series resistance and the inductance of the inductor, whereas the inductance parameter L _c has been introduced to model the increase of the series resistance R at high frequency such as observed on many different inductors taken from various IC processes. The five (5) terminals are electrically connected to both ends of the coil (terminals A and B), the tap (terminal C), the patterned ground shield (terminal D) and the substrate (terminal E). In order to include a first order account of the Eddy current losses in the substrate, the patterned ground shield and the dummy metal fill patterns, the two conductances G _p of value:

2L

Gp ⁼ TTi — _{n λ C J} , _{γ λ2} (βweii + G _sub + G _sh + G _adm ) (Y)

L _s ([ - OAbLJ L) have been added, where L _s represents the inductance of a single loop inductor with the same inner and outer diameter, G _well , G _sub , G _sh and G _adm represent the dissipative losses caused by the Eddy currents and induced in the well located on top of the substrate, the substrate, the patterned ground shield and the dummy metal fill patterns, respectively.

These Eddy current losses should only appear when sub nH inductors operate at tens of Giga Hertz (GHz). To include them in the model, we need to identify all

relevant Eddy current patterns in the vicinity of the inductor and evaluate their impact on the impedance seen at the terminals of the inductor. As illustrated in Fig. 4, we may model each Eddy current pattern as a current loop with an impedance L2/R2 and mutual inductance M with the main inductor L and approximate the impedance seen at the terminals of this device as:

Z _Eddy = R + jωL + ^- + ... (2)

Neglecting the higher order terms for the moment, the Eddy current loss yields an increase of the resistance proportional to the square of the frequency, which we can model by adding a small conductance G in parallel with the main inductor L. As long as the total amount of Eddy current losses is sufficiently small such that the above perturbation result is valid, we are able to include all of them in the model using:

wherein the summation is taken over all relevant Eddy current patterns.

Thus, for the Eddy or mirror currents induced in the high resistive silicon substrate and the moderately doped p-well located at a few microns on top of the substrate, we can them model using:

where M _f1 represents the mutual inductance between the inductor and a nested filamental current loop of radius r at depth z and R _s , _W eii and R _su b represent the sheet and bulk resistivity of the well and the substrate, respectively.

On the other hand, for dummy metal patterns of size di x d ₂ , such as shown in Fig. 5, we first need to add the contributions from all the (rectangular) Eddy current loops induced in such a metal pattern. Introducing a normalized radius x, the resistance R(x) seen by the current loop is:

R(*) = «, ₄ , % U ₁ Cl ₂ UX - (6)

where R _s ,d _m is the sheet resistivity of the metal pattern. Similarly, the mutual inductance M(x) with the main inductor is:

where M ₀ is the mutual inductance per unit of area, which we calculate from:

1 CiM Jr) Mo = -^ f^- (8)

LTir or

Integration over the pattern radius x provides the eddy current loss for a single dummy metal pattern:

G _d - ¹ \ ^M(x)2 Jx ^{1 dldl} , ^M ° (9)

^Gdm ύ J ₀ ^w ^" ύ ιβ(dl ₊ dl) R _s4m ⁽⁹⁾

A second integration over the entire area A _dm covered with a density D _dm of these dummy metal patterns then gives:

Moreover, despite the fact that the parallel bars of width w of the patterned ground shield are grounded and that Mo varies along the bar length, similar Eddy current loops such as represented in Fig. 5 are expected in these bars. Simplifying the equation (10) for di » d ₂ , and substituting d ₂ = w, the Eddy current loss in the patterned ground shield (PGS) can be considered by using:

wherein we integrate over the area A _sh covered by the shield, where D _sh is the shield density and R _s , _s h is the sheet resistivity of the shield.

In order to assess the validity of the circuit model of the invention, differentially driven octagonal symmetric inductors, with a patterned ground shield employing polysilicon bars perpendicular to the symmetry plane of the inductor, were used in this work. These inductors were fabricated in an industrial 90 nm node CMOS process with a copper backend. Using our predictive inductor model, a set of five inductors in metal 5 (330 nm Cu), and metal 6 (900 nm Cu), with low frequency inductances of 0.5, 1 , 2, 4, and 8 nH, was defined with parameters listed in Table I. In order to verify whether excellent quality factors could be realized while simultaneously meeting the strict optical density (OD), poly and metal density rules of a modern CMOS process, versions with dummy OD patterns below the polysilicon patterned shield, additional metal 1 shield bars, and various amounts of dummy metal fill patterns inside the inductor loops were also fabricated.

All inductors were characterized up to 50 GHz in two-port ground- signal-ground (GSG) configuration, such as represented in Fig. 1. De-embedding was performed using the open-short-load and pad-open-short techniques. The "pad- open-short" de-embedding was firstly used to find the actual resistance (targeted at 50 ω) and verify the capacitance (5 fF) of the load standard embedded in the load dummy, and the "open-short-load de-embedding was then applied to correct the inductor measurements. The resistance parameters used in the inductor model are listed in Table II.

Firstly, measured and simulated inductances were compared. The differences at about one tenth of the resonance frequency appear to be only a few tenths of a percent (%) as listed in the last column of table I for inductors with additional metal 1 shield bars. Given that the minute amount of inductance systematically lost in the measurement could well be caused by the inductor magnetic field seeing other inductors or the RF probes used in the measurements, we conclude that due to our analytical inductance formulation and the absence of full 90 degree corners and their current crowding effects, we can consider that our model predicts the inductance with a high accuracy.

Secondly, measured and simulated single-ended and differential peak quality factors for the 90 nm node inductors with a combined ploy and metal 1 shield were compared in Fig. 6a. Generally, the agreement is within a few percents (%). Only for the two turn inductor, the measured quality factor is somewhat larger than the simulated one. This is typical for two turn inductors and comes from the fact that both the proximity and skin effects are modeled by a single parameter.

In Fig. 6b, differential quality factor data taken on four different versions of the same 20 GHz 0.5 nH single loop inductor is collected to demonstrate the impact of Eddy current losses. Therein, the inductor A is a 20 GHz 0.5 nH single loop inductor in a conventional test environment where the inclusion of dummy metal fill patterns is blocked up to 50 μm distance of the inductor loops. For the inductor B, 3 μm squared dummy metal fill patterns were added outside the inductor up to 10 μm away from the inductor loops. For the inductor C, the polysilicon shield is additionally replaced with by a combined polysilicon and metal 1 shield. For inductor D corresponding to Fig. 1, additional 3 μm squared dummy metal fill patterns were added inside the inductor up to 10 μm distance from the inductor loops. As shown in Fig. 6b, each step going from layout A to layout D reduces the peak quality factor by about 5 percents (%), a trend well reproduced by the predictive inductor

model. It should be noted that due to the test structure parasitics, it is much more difficult to obtain reliable quality factor data at 20 GHz than for example at 3 GHz, where the quality factor of the 8 nH inductor peaks. Unfortunately, at these low frequencies, the impact of the Eddy current losses in the dummy metal fill patterns is only about 0.5 % much less than the uncertainty in the inductor resistance due to process spread. Therefore, in order to further verify the modeling of Eddy current losses, the AC differential resistance increase seen when a metal 1 shield is added is plotted versus frequency such as depicted in Fig. 7a. The dashed line represents the increase in resistance simulated when only the increase in capacitance to ground is accounted for, whereas the solid line represents the same simulation, but now with the Eddy current losses in the patterned metal 1 shield included. Similarly, in Fig. 7b, the AC resistance increase versus frequency seen when 3 μm dummy metal fill patterns are inserted up to 10 μm from the inner inductor loops is plotted versus frequency. Again, it can be seen that the model predicts the additional losses correctly.

A breakdown of the inductor losses for the five inductors aforementioned is given in Table III. The losses were calculated using the predictive inductor model at the frequency where the peak differential quality factor is obtained. As seen, the "traditional" Eddy current losses in the substrate and the p-well, although increasing linearly with frequency even for the smaller inductances, are almost negligible at typical levels of only 1 % and 3 %. The impact of the Eddy current losses in the dummy metal fill patterns and the metal 1 shield shows a steeper increase with frequency and reaches the 20 % level for the 0.5 nH inductor. However, for all inductors, the loop resistance, which can be split into DC resistance and in excess resistance due to the skin and proximity effects, remains the predominant determination parameter of the quality factor, accounting for 72 to 97 % of the inductor losses. When employing processes with thicker metal layers and lower values of

R _s ,i _nd (refer to Table II) to reduce these resistive losses, it should be noted that the Eddy current losses in dummy metal fill patterns may increase considerably since inevitably R _s ,dm will also be lower in these processes, while the process may furthermore require the use of larger dummy metal patterns. As a result, the characteristic frequencies where Eddy current loss in dummy metal fill patterns may become a point of concern could be reduced considerably compared to what is presented here in Table III for a standard 90 nm node CMOS process.

Taking this loss analysis of our five present inductors as a starting point, and using the illustrations (curves No. 1 to 5) of Fig. 8, a first step to further improve the perfor-

mance of the 20 GHz 0.5 nH type D inductor (curve No. 1), would be to reduce the metal 1 finger width of the patterned ground shield (curve No. 2) from the present value of 3 μm down to the minimum design rule of 0.12 μm. This provides a 600 fold reduction in the Eddy current losses in the metal 1 shield, and increases the peak Q from 16 to 18. A similar improvement is obtained when a polysilicon shield is used instead. The next step would be to reduce the size of the dummy metal patterns or tiles (curve No. 3) from the present 3 x 3 μm down to the minimum design rule of about 0.6 x 0.6 μm, providing a 20 fold reduction in the Eddy current losses in the tiles, and further increasing the peak quality factor to 22. Afterwards, locally blocking the well implant (curve No. 4) would further enhance the peak quality factor to 25, whereas ultimately a peak Q of 26 would be expected when the current 15 ω.cm substrate would be replaced by a high resistivity substrate (HRS) of 100 ω.cm (curve No. 5).

Thus, it may be clear from this analysis that just further enhancing the substrate resistivity without using an optimal patterned ground shield and minimum dummy metal fill sizes as well as locally blocking all well implants in an effort to improve the overall quality factors, is not effective.

It is noted that the inductive element may be a planar or non-planar single loop (turn) inductor, or a planar or non-planar spiral inductor comprising a plurality of loops (turns). Moreover, the shape of the inductive element may be a circular, square, hexagonal, octogonal, meander-shaped or any suitable other shape.

It is also noted that the invention may be applied to any RF-IC product like receiver for various wireless communication standards in CMOS090 , CMOS065 and beyond. In summary, an integrated circuit inductor structure comprising a plurality of dummy metal fill patterns as required in modern integrated circuit processes, an inductive element, a substrate and an optional patterned ground shield. Starting from our physics-based wide-band predictive compact model, a higher quality factor will be achieved when the size of the dummy metal fill patterns and the width of the patterned ground shield will be chosen as inversely proportional to the increasing operating frequency of the inductive element. The performance of such a circuit inductor can be further improved by using a high resistivity substrate as well as by locally blocking any well implant located on top of the substrate. Additionally, a higher resonant frequency can be obtained while disposing the dummy metal

fill patterns within a predetermined distance of at least three times a distance to the patterned ground shield away from the inductive element.

Finally but yet importantly, it is noted that the term "comprises" or

"comprising" when used in the specification including the claims is intended to specify the presence of stated features, means, steps or components, but does not exclude the presence or addition of one or more other features, means, steps, components or group thereof. Further, the word "a" or "an" preceding an element in a claim does not exclude the presence of a plurality of such elements.