INTEGRATED CIRCUIT AND PREPARATION METHOD THEREFOR AND ELECTRONIC DEVICE

WIPO Patent Application WO/2024/001801

A1

Some embodiments of the present application relate to the technical field of semiconductors, provide an integrated circuit and a preparation method therefor and an electronic device, and aim to improve the yield of devices in the integrated circuit. The integrated circuit can be a wafer or chip, comprising a substrate, a fin, a gate line, and a gate cutting mechanism, wherein the fin is provided on the substrate, the gate line is provided across the fin, and the gate cutting mechanism can cut the gate line into a plurality of sub-gate lines. The gate cutting mechanism comprises a first portion and a second portion connected to each other, and the second portion is located on the side of the first portion away from the substrate. The first portion comprises a first end surface connected to the second portion, the second portion comprises a second end surface connected to the first portion, and an orthographic projection of the second end surface on the substrate is located within the range of an orthographic projection of the first end surface on the substrate. Moreover, in a direction from the second portion to the first portion, a cross-sectional dimension of the first portion gradually increases, such that the cross section of the first portion is trapezoidal or tapered. The integrated circuit can be applied in a logic device and can also be applied in a memory device.

CHANG FENGYI (CN)
WU YAOZHENG (CN)

PCT/CN2023/100295

January 04, 2024

June 14, 2023

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HUAWEI TECH CO LTD (CN)

H01L29/78

CN110600471A	2019-12-20
US20190067115A1	2019-02-28
CN109786463A	2019-05-21
CN109300897A	2019-02-01
US20190326290A1	2019-10-24

BEIJING ZBSD PATENT & TRADEMARK AGENT LTD. (CN)

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