Field

This disclosure relates to a transformer for an integrated circuit. Particular embodiments relate to an impedance matching transformer and to an amplifier including an impedance matching transformer.

Background

In many electronic circuits, such as power amplifiers, a transformer is needed. These transformers transform impedance between an input port and an output port of the circuit. Power amplifiers and other devices may also require a bias signal in addition to the impedance transformation.

Conventional transformers are becoming less useful in these applications, as the demand for power amplifiers with higher signal frequencies, broad bandwidths and small device size has continued to increase. One problem with conventional transformers is that they provide desired impedance transformation within a relatively narrow bandwidth of signal frequencies. Furthermore, these transformers have relatively large sizes, which can result in high insertion losses and low power efficiency. These problems can become more significant when the transformer is required for a small-sized integrated circuit/power amplifier.

Typically, transformers are a tradeoff between bandwidth, power handling, insertion loss, transformation ratio, and physical size. There is a need for alternative transformers to provide a useful balance to these variables or an improvement to some of them.

Summary

Embodiments of a transformer include a conductor arrangement including two conductors in a bootstrap arrangement providing an impedance transformation between a first and a second port and includes a path from a third port for a bias signal, the path including at least one via formation through a substrate of the integrated circuit to connect the third port with the conductor arrangement. Embodiments of a method of simultaneously impedance matching and biasing a circuit, for example an integrated circuit amplifier, includes providing the transformer in the circuit, whereby the impedance matching is between the first and second ports and a bias signal is provided at the third port.

In some embodiments the conductor arrangement includes three conductors in series with ports at either end and a port between two of the conductors. The bias signal may be provided at an end port and traverse two of the conductors.

Further details of the transformer are included in the following paragraphs, in the context of an integrated circuit including a transformer.

Embodiments of an integrated circuit including a transformer are described. The transformer includes: a first port for receiving an input signal; a second port for outputting an output signal; a third port connected to a DC bias supply; and a conductor arrangement forming a plurality of winding portions, including a first winding portion providing at least part of a conductive path between the first port and the second port and a second winding portion providing at least part of a conductive path between the first port and the third port, wherein the first winding portion and the second winding portion are coupled in a bootstrap arrangement, the bootstrap arrangement providing an increased impedance at the second port relative to the first port for a said input signal and a said output signal comprising a radio frequency, microwave or millimetre wave signal. The conductive path between the first port and the third port includes a first via formation through a substrate of the integrated circuit and includes a coil arrangement in a plane about the via formation and the first via formation extends through the substrate transverse to the plane of the coil arrangement.

In some embodiments the conductive path between the first port and the third port includes a connection to one or more shunt capacitors.

The one or more shunt capacitors may be in the plane of the coil arrangement and the conductive path between the first port and the third port includes a second via formation through the substrate and one or more conductors between the first via formation and the second via formation. The first port, second port and third port may be in the plane of the coil arrangement. Alternatively, the connection to the one or more shunt capacitors may beat a part of the conductive path between the between the first port and the third port that is not in the plane of the coil arrangement. The one or more shunt capacitors may be stacked relative to at least part of the conductor arrangement forming a plurality of winding portions.

In some embodiments the first and second ports are in plane of the coil arrangement and the third port is not in the plane of the coil arrangement.

In some embodiments, the conductor arrangement forming a plurality of winding portions is closely coiled about the first via.

In some embodiments, along at least one axis, a space between the first via and an adjacent winding portion of the coil arrangement is substantially the same as the space between loops of the coil arrangement.

In some embodiments, the conductive path between the first port and the third port includes a series capacitor, between the coil arrangement and the second port and physically proximate the coil arrangement.

In some embodiments, the conductor arrangement forming a plurality of winding portions further includes a third winding portion arranged to form a common mode choke arrangement with the second winding portion and wherein the second winding portion is physically located between the first winding portion and the third winding portion.

In some embodiments, the integrated circuit is a Monolithic Microwave Integrated Circuit (MMIC) and wherein each said via formation extends through a semiconductor substrate of the MMIC.

In some embodiments, the transformer is impedance matched to 50 ohms at the second port.

In some embodiments, the transformer is impedance matched to less than 40 ohms at the first port.

In some embodiments, the integrated circuit further includes a power amplifier, wherein the first port is an electrical connection to an output of the power amplifier. The power amplifier may be a non-uniform distributed power amplifier. In some embodiments, the second winding portion is part of a continuous conductor from the first port to the first via formation. The first winding portion may be integral with the second winding portion and forms part of a continuous conductor across the first winding portion and the second winding portion.

Embodiments of a method of simultaneously impedance matching and biasing an integrated circuit amplifier include: at a transformer including a first port connected to an output of the integrated circuit amplifier and a second port connected to a load, impedance matching the integrated circuit amplifier and the load by a coil arrangement including a first winding portion providing at least part of a conductive path between the first port and the second port and a second winding portion in a common plane with the first winding portion and in a bootstrap arrangement with the first winding portion, the second winding portion providing at least part of a conductive path between the first port and a third port; and while amplifying, by the integrated circuit amplifier, a radio frequency, microwave or millimetre wave signal, providing to the first port, via a conductive path including the coil arrangement, a conductor at a central location of the coil arrangement extending out of the plane of the coil arrangement and the third port, a DC bias.

In some embodiments the coil arrangement further includes a third winding portion arranged to form a common mode choke arrangement with the second winding portion and wherein the second winding portion is physically located between the first winding portion and the third winding portion.

Further aspects of the present invention and further embodiments of the aspects described in the preceding paragraphs will become apparent from the following description, given by way of example and with reference to the accompanying drawings.

Brief description of the drawings

Fig. 1 shows a block diagram of a circuit including a power amplifier and a transformer connected to an output port of the power amplifier, according to embodiments of the present disclosure.

Figs. 2A and 2B show cross-sectional and top views, respectively, of an exemplary integrated circuit including a via. Fig. 3 shows a circuit diagram of a DC-via transformer including two DC-vias, according to a first embodiment of the present disclosure.

Fig. 4 shows a circuit diagram of a DC-via transformer including a single DC-via, according to a second embodiment of the present disclosure.

Fig. 5 shows a top view of a Monolithic Microwave Integrated Circuit (MMIC) chip of a DC-via transformer represented by Fig. 3.

Fig. 6 shows a top view of an MMIC chip of a DC-via transformer represented by

Fig. 4.

Fig. 7 shows experimentally obtained transfer responses (i.e. S-parameters) of transformers, including transformers of Figures 5 and 6.

Detailed description of embodiments

The following description is provided with reference to embodiments of a transformer included in an integrated circuit for a power amplifier, in particular a monolithic microwave integrated circuit (MMIC) chip. It will be appreciated that the disclosed transformer will have other applications, in particular that other applications may require the impedance matching and/or bias functions provided by the transformer. It will be appreciated that various embodiments of the present disclosure can be applicable to radio frequency (RF), microwave (MW) or millimetre wave (MMW) signals and RF/MW/MMW amplifiers/devices.

Non-Uniform Distributed Power Amplifiers (NDPAs) are a class of power amplifier that use a non-uniform distribution of transistors to achieve high output power over a broad bandwidth. NDPAs require a drain bias (or DC bias) for the amplifier circuit for amplifying a low-power input signal into a high-power output signal, which may be provided by a passive transformer. The passive transformer may also be utilised for impedance matching, for example to transform the amplifier’s relatively low internal impedance, typically less than 50 ohms, to the standard 50 ohms impedance of external systems.

The performance variables of transformers used with NDPAs for providing a DC bias and impedance matching include bandwidth, insertion loss, power efficiency and device size. In addition, the DC bias supplied by the transformer should be effectively insulated from the high frequency input signals in the NDPA circuit, which in turn can affect performance, bandwidth and insertion losses.

Types of transformers that have been used include Ruthroff broadband bandwidth transformers, and trifilar or bifilar transformers. Trifilar or bifilar transformers may be particularly useful for NDPA applications. A trifilar transformer is based on three levels of conductors (e.g. metal layers) and a bifilar transformer is based on two levels of conductors (i.e. metal layers) in the semiconductor substrate.

Embodiments of the present disclosure are directed to a transformer for an integrated circuit, described in a use case of supplying a DC bias to a power amplifier. Certain embodiments are directed to a transformer formed as an integrated circuit (IC) with its components integrated on a top-side and a bottom-side of a semiconductor substrate, such as Gallium Arsenide (GaAs) or Gallium Nitride (GaN). In some embodiments, the transformer is in the form of a monolithic microwave integrated circuit (MMIC), formed using a semiconductor substrate or on a Printed Circuit Board (PCB). The transformer is used for supplying the DC bias voltage or current to the power amplifier. In addition to providing the DC bias, in some embodiments, the transformer also provides impedance matching for matching an internal impedance of the power amplifier with an external impedance of the external device connected at an output port.

Fig. 1 shows a block diagram of a circuit 10. A low-power input RF signal is fed to an input terminal 13 of a power amplifier 11 , which signal is amplified by the power amplifier 11 to generate a high-power output RF signal. The amplifier 11 has an internal impedance, represented by block Z1 in Figure 1. A transformer 12 is connected to an output terminal 14 of the power amplifier 11. The transformer 12 has three ports. Port P1 is connected to the output terminal 14 of the power amplifier 11 and port P2 provides a physical output for the high-power output RF signal. In use, the port P2 typically connects to an external device having an impedance represented by block Z2. A DC bias 16 is supplied to the power amplifier 11 through the transformer’s port P3. In addition to supplying DC bias to the amplifier 11, the transformer 11 may also match internal impedance Z1 of the amplifier (which is generally less than 50 ohms) with the external impedance Z2 (generally 50 ohms for most standard devices) of the external device connected to port P3.

In an embodiment, the transformer 12 is formed as a Monolithic Microwave Integrated Circuit (MMIC) chip using a semiconductor substrate such as Gallium Arsenide (GaAs) or Gallium Nitride (GaN) substrate. The power amplifier 11 may however be formed on the same substrate or on a separate substrate/chip as the transformer 12. The DC bias is supplied to port P3 of the transformer 11 through at least one via, referred to herein as a “DC-via” with reference to a function to supply a DC bias.

Fig. 2A shows a cross-sectional partial view of a circuit 20 integrated on a semiconductor substrate 27. This MMIC chip includes an embodiment of a DC-via 23. Various components and ports of the circuit are located on a top-side 21 and/or bottom- side 22 of the semiconductor substrate 27 (e.g. GaAs or GaN substrate). The DC-via 23 creates an electrical connection between a top-side metal contact 25 and a bottom-side metal contact 26 of the MMIC chip. A DC bias voltage or current may be supplied from the bottom-side metal contact 26, with the DC-via 23 providing a connection to the top side metal contact 25.

The DC-via 23 may have, for example, a circular or elliptical cross-section. An internal wall/surface of the DC-via is coated with a thin layer of metal 24 such as gold (Au). The thickness of the gold layer may be, for example from 1.0 to 6.0 micrometres. In an embodiment, the DC-via may extend along the entire height of the substrate 27. The height of the substrate 27 may be, for example, within a range of 50-500 micrometres. Fig. 2B shows a partial top view the circuit 20 and shows the DC-via 23 with an elliptical cross-section. Whilst Figure 2A shows a via with one open end (the top end in the figure) and one closed end (the bottom end in the figure), either or both ends may be open or closed in any combination.

Fig. 3 shows a circuit diagram of an exemplary transformer with two DC-vias (e.g. as described with reference to Figures 2A and 2B). The transformer 30 of this embodiment includes three conductors 31 , 32, and 33 (e.g. metal layers or transformer windings). These conductor layers 31-33 may be provided on an MMIC chip in the form of strip lines, windings, or traces etc. (e.g. see transformer windings 51-53 in Fig. 5 which correspond to the conductor layers 31-33). The transformer 30 also includes two DC-vias (e.g. DC-vias 54 and 55 in Fig. 5) which form a fourth layer of conductor/metal shown by reference numeral 303. The fourth conductor layer has a first inductance L(down) 36 representing inductance of the first DC-via (e.g. DC-via 54 in Fig. 5); a second inductance L(up) 34 for the second DC-via (DC-via 55 in Fig. 5); and a line impedance Z3(35) for the other electrical characteristics of the vias and associated connections.

The conductors 31-33 and 303 are connected to one another and define a conductive path. The first conductor 31 and the second conductor 32 are coupled in a bootstrap arrangement so that a voltage drop across the second conductor 14 results in a voltage increase across the first conductor 12. This arrangement is by inductive coupling of the first and second conductors 31 and 32 and connection so that a signal responsive to the RF input signal propagates in opposite directions along the coupled conductors. In contrast the signal propagates across the second conductor 32 and third conductor 33 in the same direction, so that they are coupled in a common mode choke arrangement.

The conductive path includes a portion extending from a first end 31a of the first conductor to its second end 31b. The RF output signal is communicated along this path from the amplifier to an output. The first end 31 a of the first conductors is also connected to a first end 32a of the second conductor 32. The second end 32b of the second conductor 32 is connected to a first end 33a of the third conductor 33. Transmission lines 37 and 38 are therefore formed by the electrical connection among the three conductors 31-33 and join them in a series connection within the conductive path. In an embodiment, the conductors 31-33 are provided in the form of a coil including three metal windings connected in series. In an embodiment, the conductors 31-33 are provided in the form a single continuous wire wound in the form of a coil to form two or more windings of the transformer as shown in Fig. 5.

The second end 33b of the third conductor 33 is connected to a first end 303a of the fourth conductor 303. The circuit is configured so that the third conductor 33 can receive at its second end 303b a DC bias 304. In an alternative (bifilar) embodiment, the third conductor 33 is omitted and the second end 32b of the second conductor 32 is connected instead to the first end 303a of the fourth conductor 303. The transformer 30 includes a first port P1 , a second port P2, and a third port P3. In an embodiment, port P1 is connected an output of a power amplifier (or another electronic device/circuit that requires a DC bias and/or impedance matching). Impedance Z1 37 represents a low internal impedance (generally less than standard 50 ohms) of the power amplifier to be matched, by the transformer 30, to a high impedance Z2 38 of an external device (which may be a standard 50 ohm device/port). An RF input (RF in) signal 301 (which is the RF output of the power amplifier) is supplied at port P1 and is split into two parts at port 39. At least by connecting first conductor 31, second conductor 32 and third conductor 33 in series to form the conductive path, the transformer 30 is configured to define a passband between the first port P1 and the second port P2 and is configured to provide an impedance transformation within the passband in which the low impedance Z1 37 at port P1 is transformed into a high impedance Z2 38 at the second port P2. In this way, the transformer 30 transforms the low impedance Z1 37 at the first port P1 to substantially match the high load impedance Z2 38 at the second port P2. The amplified RF output (RF out) signal leaves at port P2 and propagates into the external device.

The fourth conductor 303, including two DC-vias and a metal connection between them, is provided between the third port P3 and the second end 33b of the third conductor. The third port P3 is used to provide a DC bias 304 that propagates through the fourth conductor 303.

In this embodiment, a series capacitive element C1 is connected in series between the second end 31b of the first conductor 31 and the second port P2. In this embodiment, a bypass capacitive element C2 is connected in shunt between the third port P3 and the first end 303a of the fourth conductor 303. The other end of the capacitive element C2 is connected directly to (i.e. shorted to) ground G1.

Fig. 5 shows a top view of an MMIC chip of a DC-via transformer 50 configured with physical connections of the DC-via transformer 30 shown in Fig. 3. The transformer 50 has three ports P1, P2 and P3, which serve the same purpose as discussed above with reference to Fig. 3. The transformer 50 has a metal coil structure including three winding portions 51-53 which correspond to three conductors 31-33 as shown in Fig. 3. The physical components implementing capacitors C1 and C2 from Figure 3 are also shown in Figure 5, marked with like references. Capacitor C2 in this embodiment is implemented by two physical capacitors.

As can be seen in part from Figure 5, the conductors of winding portion 51 and winding portion 52 form a continuous conductor. In other words, there is no intermediate component, like a bridge, to connect winding portion 51 with winding portion 52. Similarly the conductors of winding portion 52 and winding portion 53 also form a continuous conductor. Also as seen from Figure 5, in some embodiments the winding portion 51 and winding portion 52 have substantially constant cross-sectional area along their length (connections to the ports excluded). Winding portion 53 also has substantially constant cross section. In some embodiments the substantially constant cross-sectional area of winding portion 51 is substantially equal to the substantially constant cross-sectional area of winding portion 52. In some embodiments the substantially constant cross-sectional area of winding portion 51 is substantially equal to the substantially constant cross- sectional area of winding portion 52 and the substantially constant cross-sectional area of winding portion 53. The absence of an intermediate component and/or the continuous conductors may allow fabrication of a physically compact winding structure.

A fourth conductor is provided between port P3 and a second end 57 of the winding portion 53. The fourth conductor includes a first DC-via 54 and a second DC-via 55. The first DC-via 54 is a via that starts at the top-side 56 of the MMIC chip, extends down into the semiconductor substrate below the winding portions 51-53. In some embodiments the DC-via 54 ends at the bottom-side (not shown) of the MMIC chip. In other embodiments, the DC-via 54 ends at a mid-portion of the MMIC chip. The first DC-via create an electrical connection between second end 57 of the winding portion 53 located at the top-side 56 and the bottom-side (or mid-portion) of the MMIC chip. The second DC-via 55 is a via that starts at the bottom-side (or mid-portion) of the MMIC chip, extends up the semiconductor substrate and ends at the top-side 56 of the MMIC chip to create an electrical connection between the bottom-side (or mid-portion) of the MMIC chip and third port P3 located at the top-side 56. The conductor 303 includes an electrical connection between the first DC-via 54 and the second DC-via 55 (not visible in Figure 5) across the bottom-side (or mid-portion) of the MMIC chip. Apart from at the connection of the DC-via 54, the conductor 303 between DC-via 54 and DC-via 55 is electrically insulated from the winding portions 51-53. The first end of the first DC-via 54 located at the top-side of the MMIC chip may be open and the second end of the first DC-via 54 located at the bottom-side of the MMIC chip may be open or close. Similarly, the first end of the second DC-via 55 located at the bottom-side of the MMIC chip may be open and the second end of the second DC-via 55 located at the top-side of the MMIC chip may be open or close. At the bottom-side of the MMIC chip, the first DC-via is electrically connected with the second DC-via (e.g. using a metal connection). Each of the two DC-vias have a metal coating (e.g. gold coating) on the internal wall/surface of the hole of the DC-vias. A DC bias current/voltage may be supplied through port 3 located at the top-side 56 of the MMIC chip which then propagates down through metal coating of the second DC-via 55, which further propagates through the metal connection between second DC-via 55 and the first DC-via 54, which further propagates up through the metal coating of the first DC-via 54 and finally enters the second end 57 of the winding portion 53.

As can also be seen in part from Figure 5, the DC-via 54 occupies substantially the same cross-sectional area as the conductor (in this trifilar embodiment winding portion 53) to which is it connected. The use of a via therefore allows a physically compact winding arrangement, with the winding portion 53 in Figure 5 performs two U-turns so as to remain closely spaced about the DC-via 54. For instance there is insufficient free space within the centre of the windings to accommodate a second via and the space between the DC-via 54 and the winding portion 53 is small and in this case substantially the same as the space between the winding portion 53 and the winding portion 52 (and substantially the same as the space between the winding portion 52 and the winding portion 51).

Providing a physically compact winding structure may allow for increased power density per unit of cross-sectional area.

Fig. 4 shows a circuit diagram of a DC-via transformer 40 with a single DC-via (e.g. as described with reference to Figures 2A and 2B). The DC-via transformer 40 of this embodiment includes a single DC-via (e.g. DC-via 64 as shown in Fig. 6) which forms a fourth conductor indicated by reference numeral 403. The fourth conductor 403 has an inductance L(down) 46 representing inductance of the DC-via 64 (see Fig. 6) and an impedance Z3 (45). The conductors 41-43 and 403 are connected in series to one another and define a conductive path with transmission lines 47, 48 in the same manner as transmission lines 37, 38, as described with reference to Figure 3. The ends of the first conductor 41a, 41b, ends of the second conductor 42a, 42b and ends of the third conductor 43a, 43b are connected in the same configuration as the conductors 31-33 described with reference to Figure 3. Figure 4 also shows a trifilar embodiment, with a bifilar embodiment formed by omitting conductor 43.

The transformer 40 also includes a first port P1, a second port P2, and a third port P3. In an embodiment, port P1 is connected to an output of a power amplifier (or other electronic device/circuit that requires a DC bias and/or impedance matching). Impedance Z1 47 represents a low internal impedance (generally less than standard 50 ohms) of the power amplifier which is required to be matched to a high impedance Z248 of an external device (which may be a standard 50 ohm device). An RF input signal 401 (which is the RF output of the power amplifier) is supplied through port P1 and is split into two parts at the port 49. By connecting the first conductor 41 , the second conductor 42, the third conductor 43 and the fourth conductor 403 in series to form the conductive path, the transformer 40 is configured to define a passband between the first port P1 and the second port P2 and is configured to provide an impedance transformation within the passband in which the low impedance Z1 47 at the port P1 is transformed into a high impedance Z2 48 at the second port P2. In this way, the transformer 40 transforms the low impedance Z1 47 at P1 to substantially match the high impedance Z2 48 at the second port P2. The amplified RF output signal leaves at port P2 and propagates to the external device (not shown in Fig. 4).

The fourth conductor 403 (with a single DC-via) is provided between the third port P3 and the second end 43b of the third conductor. The third port P3 is used to provide a DC bias signal 404 that propagates through the fourth conductor 403.

In this embodiment, the transformer 40 includes a series capacitive element C3 connected in series between the second end 41 b of the first conductor 41 and the second port P2. In this embodiment, the transformer 40 also includes a bypass capacitive element C4 connected at node or port 403b, in shunt between the third port P3 and the first end 403a of the fourth conductor 403. The other end of the capacitive element C4 is shorted to ground G2.

Fig. 6 shows a top-side 66 of an MMIC chip of a DC-via transformer 60 which is similar to the DC-via transformer 40 as shown in Fig. 4. The transformer 60 has three ports P1 , P2 and P3 which serve the same purpose as discussed above with reference to Fig. 4. Ports P1 and P2 are located on the top-side 66 of the MMIC chip. Port P3 (not shown in Fig. 6) is located on the backside of the MMIC chip. The transformer 60 has a metal coil including three winding portions 61-63 which correspond to three conductor layers 41-43 as shown in Fig. 4.

The transformer 60 also includes a fourth conductor between port P3 and the second end 67 of the third winding 63. The fourth conductor includes a DC-via 64. The DC-via 64 is a via that starts at the top-side 66 of the MMIC chip, extends down along the height of the semiconductor substrate, and ends at the bottom-side of the MMIC chip. The DC-via 64 creates an electrical connection between the second end 67 of the third winding 63 located at the top-side 66 with port P3 located at the bottom-side of the MMIC chip.

The DC-via 64 has a metal coating (e.g. gold coating) on its internal wall/surface as previously discussed with reference to Figure 2A and 2B. The metal coating of the DC- via 64 creates an electrical connection between the top and bottom sides of the MMIC chip. A DC bias current/voltage may be passed through port 3 located at the bottom-side of the MMIC chip which then propagates up through the gold coating of the DC-via 64, which finally propagates into the second end 67 of the third winding 63.

The physical component implementing capacitor C3 from Figure 4 is also shown in Figure 6, marked with a like reference. In some embodiments the physical component or components implementing capacitor C4 from Figure 4 are located on the bottom-side of the MMIC chip. For example, capacitor C4 and the conductor between P3 and DC-via 64 may have the same configuration as capacitor C2 and the conductor between P3 and DC-via 55 (shown in Figure 3), on the bottom-side of the MMIC chip. In other embodiments C4 may be provided on the remote side of port P3 to the rest of the transformer 40, for example on a printed circuit board (PCB) on which the MMIC chip is accommodated. In these other embodiments the bottom-side of the MMIC chip includes the part of the conductor 403 between the DC-via 64 and the port P3, without any other components connected to that conductor.

It will be appreciated that at least part of the physical components implementing capacitor C4 and the conductor between P3 and DC-via 64 may be placed directly below structures on the top-side 66 of the MMIC chip. In this way a more physically compact overall structure may be realised.

Figs. 7-9 show measured and simulated transfer responses (i.e. s-parameters) of the DC-via transformer described with reference to Figure 5. The simulated results were obtained using a 3D planar electromagnetic solver. The model included details of materials used for manufacturing the DC-via transformer, which are specified using electrical parameters including the dielectric constant, magnetic permittivity, dielectric loss tangent, conductivity and physical layer thickness for: 1) the semiconductor substrate 2) each metal layer on the top-side, bottom-side of the semiconductor substrate, and 3) the intervening dielectrics which separate the metal layers on the top-side, bottom-side so that the metal layers do not electrically short. The simulation model also includes 4) details of the DC-vias connecting the metal layers at the top-side of the substrate to the back of the semiconductor/substrate, including cross-sectional size/diameter, depth (thickness of the substrate), material characteristics and thickness of the metal layer (gold layer) on the internal wall/surface of the DC-via.

Fig. 7 shows transfer responses obtained from experimental results of the DC-via transformers as shown in Figures 5 and 6 (and having a circuit diagrams as per Figures 3 and 4 respectively), terminated with 25 ohms at port P1 (amplifier side) and 50 ohms at port P2 (external). In this graph, x-axis represents frequency (in GHz units) of the RF signal fed to port P1 of the DC-via transformer and y-axis represents the amplitude of the S11, S22 and S21 S-parameters (in dB). The parameters for the transformer of Figure 5 are represented by long dashes and the parameters for the transformer of Figure 6 are represented by short dashes. Figure 7 also shows in solid lines S-parameters for a transformer using a bridge connecting the innermost winding portion to the DC bias port instead of the via or vias, which shows comparable performance of the via embodiments with a bridge embodiment. The amplitude of S11 and S22 show that the transformer exhibits a good match to 25 ohms internally and 50 ohms at the external port. For example, both have a negative magnitude greater than about -6 dB over a frequency range of about 5 to 25 GHz. The amplitude of S21 is close to 0 dB (i.e. within about -1 dB) for most of the frequency range of interest, including between about 6 GHz to about 23 GHz.

As used herein, references relating to orientation, for example “top”, “bottom”, “up” and “down” are illustrative only and are not intended to limit the disclosed structure to use in any particular orientation.

As used herein, the terms “first”, “second”, “third” and so forth refer to instances of the entities referred to and do not indicate any required order, whether in time, space or otherwise. Also, reference to a “first” entity does not in itself imply or require the existence of another (i.e. “second”) entity.

It will be understood that the invention disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text or drawings. All of these different combinations constitute various alternative aspects of the invention.