Title:
INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2022/241785
Kind Code:
A1
Abstract:
An integrated circuit, which is used to optimize the structure of pipelines, and reduce the reserved cache of downstream modules while ensuring the normal operation of a chip, thereby reducing the resource overhead of the entire chip caused by the pipelines. The integrated circuit comprises a first module, a second module and a data forwarding circuit. The data forwarding circuit comprises multiple stages of first registers and a plurality of delay trigger apparatuses that correspond one-to-one with the multiple stages of first registers. The second module is configured to: receive data sent by the first module from the data forwarding circuit by means of caching; and send a notification message to the data forwarding circuit when cache free capacity is less than or equal to a set value. Each stage of first registers among the multiple stages of first registers is used to perform stage by stage forwarding on the data sent by the first module. Each of the plurality of delay trigger apparatuses is used to control the corresponding first registers to be disabled after the data forwarding circuit receives the notification message.
Inventors:
YIN HAIYOU (CN)
GAO ZHENGDONG (CN)
YIN BEI (CN)
GAO ZHENGDONG (CN)
YIN BEI (CN)
Application Number:
PCT/CN2021/095308
Publication Date:
November 24, 2022
Filing Date:
May 21, 2021
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
G06F9/38
Foreign References:
| CN108334338A | 2018-07-27 | |||
| CN113032312A | 2021-06-25 | |||
| CN1752925A | 2006-03-29 | |||
| CN107770090A | 2018-03-06 | |||
| US20120110304A1 | 2012-05-03 |
Attorney, Agent or Firm:
TDIP & PARTNERS (CN)
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