Title:
INTEGRATED VOID FILL FOR THROUGH SILICON VIA
Document Type and Number:
WIPO Patent Application WO/2011/090912
Kind Code:
A3
Abstract:
A microelectronic assembly and method of forming a through hole extending through a first and second wafer are provided. The first and second wafer have confronting faces and metallic features at the faces which are joined together to assemble the wafers. A hole can be etched through the first wafer until a gap is exposed between the confronting faces. The hole can have a first wall and a second wall sloping inwardly from the first wall to an opening through which the gap is exposed. Material of the first or second wafers exposed within the hole can then be sputtered creating a wall between the confronting faces. The hole can be etched so as to extend the first wall through the first wafer, such that the wall of the hole extends continuously from the first wafer into the second wafer. An electrically conductive through silicon via can then be formed.
Inventors:
VOLANT RICHARD P (US)
FAROOQ MUKTA G (US)
PETRARCA KEVIN S (US)
FAROOQ MUKTA G (US)
PETRARCA KEVIN S (US)
Application Number:
PCT/US2011/021446
Publication Date:
November 03, 2011
Filing Date:
January 17, 2011
Export Citation:
Assignee:
IBM (US)
VOLANT RICHARD P (US)
FAROOQ MUKTA G (US)
PETRARCA KEVIN S (US)
VOLANT RICHARD P (US)
FAROOQ MUKTA G (US)
PETRARCA KEVIN S (US)
International Classes:
H01L23/12; H01L21/60; H01L23/48
Domestic Patent References:
| WO2009017835A2 | 2009-02-05 |
Foreign References:
| US20090278251A1 | 2009-11-12 | |||
| US20060040471A1 | 2006-02-23 | |||
| KR20090054123A | 2009-05-29 |
Attorney, Agent or Firm:
SCHNURMANN, Daniel, H. (2070 Route 52Bldg. 321, M/D 48, Hopewell Junction NY, US)
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