Title:
INTEGRATION OF SELF-ALIGNED TRENCHES IN-BETWEEN METAL LINES
Document Type and Number:
WIPO Patent Application WO2007083237
Kind Code:
A8
Abstract:
The present invention provides an improved method of forming air cavities to overcome IC via-misalignment issues. The method of forming air cavity trenches in-between metal lines of an integrated circuit includes the steps of partially removing (42) an intertrack dielectric deposited on an interconnect structure surface to control the height between the top surface of a metal line of the interconnect surface and the surface of the intertrack dielectric; depositing (44) a dielectric liner on the interconnect surface; removing (46) at least part of the dielectric liner on the interconnect surface; successively repeating (48) the deposition of the dielectric liner and the removal of the dielectric liner on the interconnect surface in so far as the interconnect surface is sufficiently protected by a remaining dielectric liner for forming of the plurality of air cavity trenches; and forming (50) at least one air cavity trench in-between the metal lines by etching the intertrack dielectric material.
Inventors:
TORRES JOAQUIN (FR)
GOSSET LAURENT-GEORGES (FR)
GOSSET LAURENT-GEORGES (FR)
Application Number:
PCT/IB2007/000162
Publication Date:
December 27, 2007
Filing Date:
January 11, 2007
Export Citation:
Assignee:
ST MICROELECTRONICS CROLLES 2 (FR)
KONINKL PHILIPS ELECTRONICS NV (NL)
TORRES JOAQUIN (FR)
GOSSET LAURENT-GEORGES (FR)
KONINKL PHILIPS ELECTRONICS NV (NL)
TORRES JOAQUIN (FR)
GOSSET LAURENT-GEORGES (FR)
International Classes:
H01L21/768
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