Title:
INTERFACE LAYER REDUCTION METHOD, METHOD FOR FORMING HIGH DIELECTRIC CONSTANT GATE INSULATING FILM, HIGH DIELECTRIC CONSTANT GATE INSULATING FILM, HIGH DIELECTRIC CONSTANT GATE OXIDE FILM, AND TRANSISTOR HAVING HIGH DIELECTRIC CONSTANT GATE OXIDE FILM
Document Type and Number:
WIPO Patent Application WO/2011/068096
Kind Code:
A1
Abstract:
When a high dielectric constant film is formed on a substrate as a gate insulating film, an interface layer of SiOx or the like is formed at the interface between the gate insulating film and the substrate, thereby lowering the effective dielectric constant of the gate insulating film.
Disclosed is an interface layer reduction method for reducing the thickness of an interface layer, which comprises (a) a step of forming an oxide film of a first metal on a semiconductor layer with an oxide film of the semiconductor lying therebetween so as to serve as an interface layer; and (b) a step of forming an oxide film of a second metal on the oxide film of the first metal, said second metal having a larger valence than the first metal.
Inventors:
UMEZAWA NAOTO (JP)
CHIKYO TOYOHIRO (JP)
NABATAME TOSHIHIDE (JP)
CHIKYO TOYOHIRO (JP)
NABATAME TOSHIHIDE (JP)
Application Number:
PCT/JP2010/071353
Publication Date:
June 09, 2011
Filing Date:
November 30, 2010
Export Citation:
Assignee:
NAT INST FOR MATERIALS SCIENCE (JP)
UMEZAWA NAOTO (JP)
CHIKYO TOYOHIRO (JP)
NABATAME TOSHIHIDE (JP)
UMEZAWA NAOTO (JP)
CHIKYO TOYOHIRO (JP)
NABATAME TOSHIHIDE (JP)
International Classes:
H01L21/316; H01L21/8238; H01L27/092; H01L29/78
Foreign References:
| JP2007173796A | 2007-07-05 | |||
| JP2003204058A | 2003-07-18 |
Attorney, Agent or Firm:
SHIODA Shin (JP)
Shin Shioda (JP)
Shin Shioda (JP)
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