INTERFEROMETER CONFIGRATION HAVING A FEEDBACK LOOK

Introduction

Field of the Invention

The invention relates to optical data processing.

Prior Art Discussion

Referring to Fig. A, it is known to provide a Mach-Zehnder interferometer (MZI) with a semiconductor optical amplifier (SOA) in each arm. Such a device can act as an AND or an XOR (exclusive OR) gate and, if the phase difference between the interferometer arms is adjusted to invert the output, it can also act as a NAND or XNOR.

An AND operation may be obtained between a control input at A and a probe signal at C. The phase difference between the two arms is initially set to π radians so that the two components of the probe signal interfere destructively and produce no output. When a control input is applied to A, however, cross-phase modulation in SOAl changes the phase difference (ideally to 0 radians), allowing constructive interference and hence producing an output. Since the output requires an input at both A and C (the input at A does not itself reach the output, being blocked by a filter), it represents the AND function.

XOR operation is obtained between control inputs to A and B when a continuous- wave (CW) probe is applied to C. The phase difference between the two arms is set to π radians, as for the AND gate, and hence the interferometer transmits and produces an output whenever an input is present at A only. When an input is applied to B only, the phase difference also changes due to cross-phase modulation in SOA2, but in the opposite sense, and again an output is obtained. However, no output is obtained when

inputs are applied to A and B simultaneously because equal cross-phase modulation is induced in both SOAs, giving no change in the phase difference and hence no output.

While such operations are useful in some applications the invention is directed towards providing for more comprehensive data processing.

References

1. "10 Gbit/s all-optical regenerative memory using single SOA-based logic gate", R. J. Manning et al, Electronics Letters, Volume: 35 , Issue: 2, page(s): 158 - 159

SUMMARY OF THE INVENTION

According to the invention, there is provided an optical data processing system comprising a plurality of optical amplifiers connected in an interferometer configuration having inputs A and B, and a feedback loop to a common amplifier input C, and wherein the interferometer is configured to generate an output indicating if a target pattern applied to the interferometer input B is detected in a data sequence applied to the interferometer input A.

In one embodiment, the system further comprises a regenerative device in the feedback loop.

In one embodiment, the feedback loop includes an OR gate to receive the feedback and an initialisation pulse, and the system further comprises an XOR gate to receive A and B.

In one embodiment, said XOR gate is connected to the feedback loop via an AND gate.

In one embodiment, phase difference between the arms of the interferometer are set to give constructive interference in the absence of inputs at A and B.

In one embodiment, the system further comprises an input for receiving an initialising pulse to C.

In one embodiment, the system comprises means for generating in a first circulation an output which is an «-bit sequence presented as data in the first circulation if the first target bit is 1, and the inverse of the sequence if the first target bit is 0.

In one embodiment, the system comprises means for receiving each successive bit of the target pattern presented to the input B in synchronisation with the corresponding rc-bit data circulation sequence.

In one embodiment, the system comprises means for generating an output if a current bit in the repeated data sequence is equal to the current bit in the target pattern and the preceding bits in the sequence were equal to the preceding bits in the target pattern.

hi one embodiment, an output pulse during the final circulation of the repeated data sequence indicates that the target pattern was found in the sequence.

hi one embodiment, the position of the output pulse, or pulses, during the final circulation of the repeated data sequence indicates the position of the target pattern in the sequence.

hi one embodiment, the system comprises means for repeating n bits of the data and for receiving the target pattern applied at a data bit rate/«.

hi another aspect, the invention provides a method of identifying a target pattern in an «-bit data signal having a repetition period equal to n times the bit period, the method being performed using any system as defined above, the method comprising the steps of inputting the data signal to input A, and inputting the target pattern to input B

In one embodiment, the target pattern bit period is substantially equal to the data signal repetition period.

In one embodiment, the method comprises the further step of inputting an initialisating pulse to the input C.

In one embodiment, the initialising pulse is a continuous wave probe for the duration of the pulse.

In one embodiment, the initialising pulse has a pulse length of the data signal repetition period.

hi one embodiment, the system generates in a first circulation an output which is an n- bit sequence presented as data in the first circulation if the first target bit is 1 , and the inverse of the sequence if the first target bit is 0.

In one embodiment, system receives each successive bit of the target pattern presented to the input B in synchronisation with the corresponding rø-bit data circulation sequence.

hi one embodiment, the system generates an output if a current bit in the repeated data sequence is equal to the current bit in the target pattern and the preceding bits in the sequence were equal to the preceding bits in the target pattern.

In one embodiment, an output pulse during the final circulation of the repeated data sequence indicates that the target pattern was found in the sequence.

In one embodiment, the position of the output pulse, or pulses, during the final circulation of the repeated data sequence indicates the position of the target pattern in the sequence.

DETAILED DESCRIPTION OF THE INVENTION

Brief Description of the Drawings

The invention will be more clearly understood from the following description of some embodiments thereof, given by way of example only with reference to the accompanying drawings in which:-

Fig. 1 is a diagram illustrating an optical data processing system of the invention; and

Figs. 2 and 3 are truth tables illustrating operation of the system;

Fig. 4 is a set of waveforms for data from the table of Fig. 2; and

Fig. 5 is a diagram showing a logic gate equivalent to the system

Description of the Embodiments

Referring to Fig. 1 an optical data processing system 1 comprises two semiconductor optical amplifiers SOAl and SOA2. There are inputs A and B for the amplifiers SOAl and SOA2 respectively and a common input C to both. The output is fed back to C. The input A is fed by a re-circulating loop 2 which receives a high speed data stream. The common input C is also connected to receive an initialising pulse. For ease of understanding, Fig. 5 shows an equivalent circuit.

The high speed digital optical data signal is received at the input to the re-circulating loop 2. The loop 2 re-circulates an rc-bit sequence from the high speed input data N times in order to search the sequence for an iV-bit target pattern. The target pattern is received at B, slowed down by division by n. In the example shown in Fig. 1, n = 8 and N = A. Both an initialising pulse and the feedback are received at the common input C.

The system detects a target pattern in the n-bit sequence at A. It operates very effectively to do this even though the data is at a very high speed, which would in the prior art have caused major problems because it is very difficult to search for a pattern and synchronise at a high bit rate

An H-bit sequence from the high-speed digital optical signal that is to be searched for a target pattern is repeated N times, by a recirculating loop 2, where N is the number of bits in the target. The technique for storing data in a recirculating loop is as described in Ref. 1. Synchronisation for selecting the sequence from the input data to be switched into the loop may be obtained by a time delay, which may be initiated either by the start of a data packet or by the detection of a special synchronisation word included in the data. The repeated sequence is applied to input A. During the first pass of the sequence, lasting nT, where T is the bit period, a pulse of length nT whose amplitude represents the value (0 or 1) of the first bit in the target pattern is applied to input B. A pulse of the same length but fixed amplitude is applied to C as an initialising pulse. Since the initialisation pulse and the target pattern are at \ln of the input data rate, they are relatively easy to generate, for example, by direct modulation of semiconductor lasers.

The phase difference between the two arms of the interferometer is set to give constructive interference in the absence of inputs to A and B. Thus, during the first period nT, the interferometer acts as an XNOR gate with the initialising pulse providing a CW probe input at C. If the first bit of the target pattern is a 1, then the output is equal to the n-bit sequence applied to A; but if the first bit of the target is a 0, the output is the inverse of the sequence. Each 1 in the output therefore indicates where a bit in the sequence is equal in value to the first bit of the target. Put another way, on the first pass, if the target is high, then the output is all the bits where the data is also high, as shown in the left hand frame of the output in Fig. 1.

During the second pass of the rc-bit sequence, the second bit of the target pattern is presented to input B. Thus the interferometer transmits whenever the sequence has the same value as this second bit. However, the input at C is now the output delayed by (n+l)T, i.e. one bit more than the second repeat of the n-bit sequence. Clearly the interferometer can only produce an output when it has an input, thus a 1 in the output now indicates where a bit in the sequence is equal to the second bit in the target pattern AND the preceding bit in the sequence was equal to the first bit in the target.

On each circulation of the output through the interferometer, the Is are only transmitted where the bit in the sequence matches the next bit in the target. After N circulations, each 1 shows an occurrence of the complete target pattern and indicates its position.

As shown in Fig. 1, if there is an output in the last re-circulation, the pulse shows the position of the target. The logic gate equivalent of the optical system is shown in Fig. 5.

In more detail, an optical gate configured as shown in Fig. A acts as an exclusive NOR gate if the lengths of the interferometer arms are adjusted to give constructive interference at the output. The gate will then transmit the input C to the output in the absence of inputs at A and B. It will also transmit if identical inputs are presented to A and B, because the phase changes induced in the two SOAs will be equal and so the signals in each arm will still add constructively at the output. However, if an input having the appropriate power level is presented to just one of the inputs A or B, a π- radian phase shift will be induced in that arm and the interferometer will block input C. The operation of the gate may be represented by the following Boolean logic expression:

Y = C _* (A =B) i

where A = B takes the value 1 (true) when A and B are equal or 0 (false) otherwise, i.e. it represents the exclusive NOR operation. The dot following the C indicates AND.

An initialising pulse is applied to C during the first pass (numbered 0) of the rc-bit sequence, thus all the bits C _{0 k} = 1 . The output of the first pass is therefore given by:

Y _0λ = (λ == B ₀ ) 2

(Note that X _m,k denotes the k ^xh bit of parameter X on the m* pass, k and m take integral values from 0 to n-\ and 0 to JV-I respectively. However, in the case of A, which is the same on every pass, the redundant m subscript is omitted; and in the case of B, which remains constant during each pass, the k subscript is similarly omitted)

Hence, an output pulse occurs whenever a bit in the n-bit sequence matches the first bit of the target. The top part of Table 1 (Fig. 2) shows the output in response to an example sequence and a target pattern whose first bit is 1.

On the next pass of the n-bit sequence (pass number 1), the previous output is fed back to C with a 1-bit delay relative to the sequence at A. Thus C is given by:

C - Y

■ ^■ ■ C _uk = [A^ = B ₀ )

The output of pass 1 is obtained by substituting equation 3 into 1:

After this pass, an output pulse occurs whenever a successive pair of bits in the n-bit sequence match bits 1 and 2 of the target (1 0 in the example in Table 1 of Fig. 2).

Similarly, on subsequent passes the previous output is fed back to C with a 1-bit delay and transmitted by the gate when A = B. After JV passes, the output is given by:

YN-U AA-N,X = Bo )' (A _k - _N+ 2 = 5 ₁ )- ^« (λ-i = BS-I HA = BN-X ) ⁵

That is, an output pulse occurs when JV bits in the repeated sequence applied to A match the target pattern applied to B. The pulse indicates not only the presence of the pattern, but also its position in the sequence.

The evolution of feedback signal, C, and the output, Y, through 4 passes is shown in Table 1 in Fig. 2 and also as waveforms in Fig. 4, along with the repeated sequence, A, and target pattern, B. Table 2 of Fig. 3 shows the results with the same target and two other example sequences.

If the bit period of the n-bit sequence is less than the effective nonlinear recovery time of the SOAs, then the optical gate can be operated in differential or push-pull mode by also connecting the sequence to input B after a delay of At which is less than T. The additional connection is indicated by the dashed line in Fig. 1. A similar connection for the target pattern input is not required because this input is received at a lower speed.

Because of the reduced speed at which the target pattern is input to the system (sequence bit rate/n), it may be generated by relatively low speed electronics and will normally be possible to directly modulate the bias current to a laser diode. As an alternative to the optical input to B, it may be possible to modulate the bias current of one or both SOAs with the target pattern to obtain an equivalent change in the phase difference in the arms of the interferometer.

Since the number of circulations of the sequence and interferometer output is equal to the number of bits in the target pattern, N, when N is large it may be advantageous to incorporate a regenerative device in the feedback loop to C. Alternatively, N may be reduced by dividing the target into smaller patterns and implementing parallel systems to search for all the sub-patterns simultaneously. Reducing N would have the additional advantage of reducing the delay before the result is obtained.

In the system as described above, the difference between the output feedback delay and the repetition period of the input sequence is 1 bit. Other delay differences could be used. For example, -1 bit would require the target to be presented in the reverse order. Larger positive or negative differences would skip bits in the sequence, which could be useful if, say, only parity or other significant, regularly spaced bits were to be checked.

The repeated n-bit sequence can include some additional bits at the start and finish whose content is unimportant in order to provide a guard band. A guard band would allow time for switching between successive bits of the target pattern at input B and relax the synchronisation requirements between the target pattern and the sequence repetitions.

The output indicates the presence and positions of occurrences of a target pattern in the n-bit sequence. Thus the system may be used to search for a particular address or sub-address or for other significant content in a packet of data. It could also generate a synchronisation pulse by detecting a known preamble pattern.

The system does not require any locally generated high-speed clock or other signal and does not require bit-level synchronisation with the incoming data.

The target pattern is generated at 1/n x the incoming data rate, which will normally bring it within the capabilities of standard electronics and permit direct modulation of a laser diode or of the SOA bias currents. The target is therefore simple to change. A guard band may be introduced into the repeated sequence to allow for the consequently slower rise and fall times of the target.

In order to search an n-bit sequence for an N-bit target, the sequence must be repeated N times, which will take a time oinNT. As a result of this latency, it is not possible for a single system to search all bits in a continuous bit stream. However, it should be possible to examine a significant part of a data packet, e.g. the address, within the packet duration.

However, the use of recirculation to permit a logic operation that combines high-speed and low speed inputs is advantageous.

The following are some applications of the system.

- Address recognition in optical packet communication systems. The system could be used to recognise the destination address or a subset of the address field for switch control.

- Quality of service (QoS). Distinguishing packets according to their QoS bit settings.

- Frame synchronisation. Detecting the position of a known word included in a data stream for synchronisation purposes.

- Security. Filtering packets with specified content or with suspect source addresses.

The invention is not limited to the embodiments described but may be varied in construction and detail.