DESCRIPTION

IrOx NANOWIRE NEURAL SENSOR

TECHNICAL FIELD

This invention generally relates to integrated circuit (IC) fabrication and, more particularly, to a fine resolution sensor with an iridium oxide nanowire neural interface .

BACKGROUND ART

Figs. IA through 1 C depict the placement of optical electrodes, using epiretinal and subretinal approaches (prior art) . Studies show that blind patients with retinitis pigmentosa and masular degeneration can observe a visual percept induced by the direct electrical stimulation of the retina. Recently, retinal prosthesis development has progressed along two directions. The epiretinal approach places electrode in the vitreous fluid, attached to the surface of the retina, while the subretinal approach places electrodes on the outside of retina, wedged between the photoreceptors and the pigment epithelium. Fig. 1 C shows the electrode positions for both type of retina prosthesis.

One major difficulty with the epiretinal approach is that the tissue has a very high resistance to electrical stimulation. This high electrical resistance is due to the fact that the

retinal is covered by the inner limiting membrane, similar to the blood-brain barrier, and it is impermeable to many types of ions. Since electrical stimulation depends on electrical current building an electrical field across the target nerve cell, a high-resistance barrier in the stimulation pathway prevents current passage . Thus, current is diverted away to other, lower-resistance tissues. To compensate for this loss, the epiretinal approach requires a much larger charge at the electrode surface, to achieve the same stimulation level on the target tissue as a conventionally functioning eye . In human trials, a net charge of - I uC (micro-Coulomb) is required for the epiretinal approach, a very high charge for neural stimulation, when compared to 50 nC, which is the level typically required for central nervous system stimulation and subretinal stimulation.

One way to overcome the high-impedance barrier of the epiretinal approach is to penetrate the inner limiting membrane. Arrays of sharp electrodes have been fabricated from silicon and have been used for this purpose. Recently, new techniques promise nano-scale piecing wire electrodes, which can be formed by electrodeposition on a glass substrate contoured to fit the retina.

The subretinal prosthesis avoids the high-impedance barrier problem, by installing electrodes behind the retina. The electrodes are also very close to the bipolar cells,

allowing easy (low-charge) stimulation. Low thresholds in the range of 2.8 to 100 nC / cm ² have been reported. However, 178 uC/ cm ² is a more realistic number. Subretinal prostheses requires that all components be fitted behind the retina, with the circuits integrated with the electrodes. Power is transferred into the eye via light, which in theory is received by integrated photovoltaic cells, to activate the circuitry. The power output needs to be strictly controlled, since heat dissipation is limited in the subretinal space, and overheating can easily damage the retina.

One technical challenge is the trade-off between electrode density and stimulation charge. Although the total charge injection required to elicit a visual percept is fixed, the maximum charge an electrode can deliver is limited by its surface area. Surpassing this charge density threshold generates undesirable and irreversible electrochemical reactions. In order to elicit a visual percept, the charge density requirement dictates that the electrode must have a total surface area of 1 mm ² . When considering the limited area of the retinal implant, this constraint translates into a resolution of 5x5 (25 pixels) . However, a visual resolution of at least 25x25 pixels (625 pixels) is desired for recovery of functional sight.

To inject more charge without hydrolysis, an electrode made from a material with a higher injection limit can be

used, such as iridium oxide (IrO _x ) . As a biocompatible electrode material, IrO _x has advantages over Au and Pt. Au quickly dissolves when a high potential is applied. Pt has the longest history as an electrode material and is the best characterized. Compared to IrO _x , the performance of Pt is limited because it cannot sustain as much reversible faradic charge, and it catalyzes water electrolysis at low voltages, limiting its charge-injection capability. Compared to Pt, an IrO _x electrode can inject much more charge for a given voltage swing, by cycling iridium through many oxidation states.

Because iridium can exist in many valence states with an insignificant change in atomic size, an iridium electrode can cycle from metallic form (Ir) to higher oxidized form (Irθ4) reversibly, allowing it to have a high charge-injection limit of 1 mC / cm ² . Using cyclic voltammetry with scan rates of

0.06V/ s or slower, a charge injection of > 25 mC / cm ² can often be obtained. This behavior is attributed to IrO _x porous structure, which requires ionic species to diffuse into deep recessed regions to access the full surface area, as well as due to its many oxidation states, requiring the completion of one state change before proceeding to the next reaction. IrO _x is especially ideal for applications with slower stimulation waveforms. For neural stimulation, a current pulse longer than 200 us can be employed. Furthermore, IrO _x needs to be biased so that its oxidation state is between Ir ³⁺ and Ir ⁴⁺ to

prevent dissolution that occurs at metallic or higher oxidation states. However, because it relies heavily on faradic reactions, IrOx is slower in delivering current.

A second approach to increasing electrode charge- injection involves enlarging the electrode surface area. The surface area of an electrode is a strong function of its geometry. The area of a solid post electrode can be increased by a factor of 10 easily if it is formed into an array of nanowires/tubes/rods. Fig. 2 is a schematic diagram modeling the interface between an electrode and chemically active solution (prior art) . Electrodes pass charge mainly through two mechanisms: faradic reactions and capacitive charging. Capacitive charging is the accumulation of charge at the interface between electrons in a metal electrode and ions adjacent to the electrode in a solution, and is represented by CE. A faradic reaction is the transfer of electrons with ions in a solution by a redox reaction of metal species, and is represented by RE. Both the capacitive and faradic components increase linearly with the electrode area because more charge can accumulate at the interface area and be transferred through chemical reactions by increasing the size of the electrode. This larger electrode can be modeled as having a smaller R _E and bigger CE, leading to an increased electrode current at a given potential. Pulses of either

constant voltage or current can be used for electrical stimulation. Most frequently, pulses of constant current are used.

Fig. 3 is a partial cross-sectional view comparing a conventional flat electrode with an electrode array (prior art) .

Micro-machined neural-stimulating electrode array technology has also been researched. The micro-machined electrode has the advantage of providing additional surface area to decrease the current density, while increasing the electrode density and avoiding material corrosion. However, a key issue to be resolved is the fabrication of an electrode array that can conform to the concave shape of the foveal pit. For example, such as array would need to be formed on a flexible substrate (e.g. , polyimide) . The conventional techniques as illustrated in Figs. 1 through 3 are disclosed, for example , in US Patents No . 5109844 , 5215088, and 4628933.

Another limitation associated with micromachining technology is size, as the individually machined electrodes cannot be made to a nano-size resolution. Even if a template of nano-sized structures could be micro-machined, plating an array of nanostructures, with a noble metal for example, in a sufficiently high aspect ratio is a big challenge. Micro- machined electrodes are normally formed from a thick film that is deposited using a physical vapor deposition (PVD)

process or electrode plating. In either case, the resultant film, and micro-machined electrode post are typically a polycrystalline material.

Thus, research is ongoing in the investigation of nanowire-based neuron electrode arrays that can be used to promote the growth of subcellular highways via controlled electrical stimulation. Combined with quantum dots assisted imaging technology, these subcellular highways have potential in image transportation. Nanowire neuron arrays also have the potential to guide movement of drugs and other factors on subcellular highways. These applications may become important in therapy for conditions involving the defective transport of neurons and neurodegenerative disease, for example : Alzheimer's, Huntington's, Parkinson's, and acute brain injury.

Some challenges facing c nventional neuron stimulating and recording electrodes are the lack of resolution in micro- fabricated structures. Poor resolution makes in impossible to stimulate subcellular regions of a single cell. This issue can be addressed with the use of grown nanostructures.

Experiments with conductive carbon nanotubes (CNTs) have been conducted to test their effectiveness in neural guidance. However, CNTs are prone to bending and warping, and lack the robustness required for repeatable sensitive electrical measurements.

On the other hand, IrO _x nanowire-based neuron electrode have a better surface to volume ratio, as compared to CNTs, as well as a high resolution stimulation, biocompatibility, and ability to grow on transparent conducting electrodes such as ITO , Snθ2, ZnO and Tiθ2 with or without any doping.

Single-crystal Irθ2 nanowires/ rods/ tips have a much longer life than polycrystalline Irθ2, due to their higher chemical reaction resistance. Single-crystal IrO _x nanostructures also have a higher conductance than polycrystalline Irθ2, so they can pass through current more efficiently. However, it is difficult to form single-crystal Irθ2 films using conventional PVD or electrode plating methods. Irθ2 nanostructures can be formed using a solution method, but these structures have a low mechanical strength and poor crystal quality. Vapor phase transport methods can also be used to form Irθ2 nanostructures, but this process requires high substrate temperature, and it is not suitable for use with glass and polyimide substrates. A technology that can grow free standing highly crystallized nanowires/ tubes/rods array of IrO _x on highly resolved areas of electrode would be useful in the fabrication of a neuron interface.

DISCLOSURE OF INVENTION

This application describes the fabrication process for an IrO _x nanowire-based neuron electrode for stimulating and recording neuron activities, and for use in therapy for neurodegenerative diseases. Compared to micromachined neuron electrodes, IrO _x nanowires have an improved surface to volume ratio, and a higher resolution - making them more capable of stimulating targeted areas. An IrO _x nanowire sensor is biocompatibility and can be grown on a transparent conducting electrode for imaging applications. Accordingly, a method is provided for forming an iridium oxide (IrO _x ) nanowire neural sensor array. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, Siθ2, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, Snθ2, ZnO, Tiθ2, doped ITO , doped SnO2, doped ZnO , doped Tiθ2, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes in the dielectric layer and exposing regions of the conductive layer. IrO _x nanowire neural interfaces are grown from the exposed regions of the conductive layer. Each of the IrO _x nanowire neural interfaces preferably has a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval. In one aspect, the substrate is a substrate chip with

edges, and prior to forming the dielectric layer, the conductive layer is etched to form electrodes, probe pads along the chip edges, and traces connecting the electrodes to the probe pads. Then, the step of forming contact holes in the dielectric layer may include forming a neural interface contact hole overlying each electrode and a probing pad contact hole, which overlies and exposes regions of each probing pad. IrO _x nanowires can additionally be grown from the exposed regions of the probing pads. Additional details of the above-described method and an

IrO _x nanowire neural sensor array are presented below.

BRIEF DESCRIPTION OF DRAWINGS

Figs . IA through 1 C depict the placement of optical electrodes, using epiretinal and subretinal approaches (prior art) .

Fig. 2 is a schematic diagram modeling the interface between an electrode and chemically active solution (prior art) . Fig. 3 is a partial cross-sectional view comparing a conventional flat electrode with an electrode array (prior art) .

Fig. 4 is a partial cross-sectional view of an iridium oxide (IrO _x ) nanowire neural sensor array.

Figs . 5A and 5B are plan and cross-sectional views, respectively, depicting a variation of the neural sensor array of Fig. 4.

Figs. 6A and 6B are plan views depicting other variations of the neural sensor array of Fig. 4.

Figs. 7A through 7E are partial cross-sectional views depicting steps in the fabrication of an IrO _x nanowire neural sensor.

Fig. 8 is a flowchart illustrating a method forming an IrOx nanowire neural sensor array.

BEST MODE FOR CARRYING OUT THE INVENTION Fig. 4 is a partial cross-sectional view of an iridium oxide (IrO _x ) nanowire neural sensor array. The array 400 comprises a substrate 402 and a conductive layer 404 overlying the substrate 402. A dielectric layer 406 overlies the conductive layer 404. Contact holes 408 with sloped walls 410 are formed in the dielectric layer 406, exposing regions 412 of the conductive layer 404. IrO _x nanowire neural interfaces 414 are shown, grown from the exposed regions 412 of the conductive layer 404. With respect to IrO _x , typically x is < 4. Although only 3 interfaces 414 are shown, the array is not limited to any particular number of interfaces.

A nanowire may alternately be known as a nanostructure, nanorod, nanotip, or nanotube.

The average IrO _x nanowire 416 has an aspect ratio in a range of about 1 : 1 to about 1 : 1000. As used herein, aspect ratio is defined as the ratio of the nanowire height 418, to the

nanowire diameter or width 420 at proximal end 422 (base) attached to the conductive electrode 404. The IrO _x nanowires have an average height 418 in the range of about 10 nanometers (nm) to about 10 micrometers (μm) . The IrO _x nanowires have an average proximal end diameter 420 in a range of about 1 nm to about 1 μm.

In one aspect, each IrO _x nanowire neural interface 414 has a cross-section 424 in the range of 0.5 to 10 micrometers. If seen in a plan view from above (not shown) , the nanowire neural interfaces would have a shape such as a rectangle, square, circle, or oval. However, the invention is not limited to any particular shape. Advantageously, the small cross- sectional area of the neural interface 4 14 permits an interface to made to biological features as small as individual cells. The conductive layer 404 is a material such as ITO, SnO ₂ ,

ZnO, TiO ₂ , doped ITO, doped SnO ₂ , doped ZnO, doped Tiθ2 , TiN, TaN , Au, Pt, or Ir. The substrate 402 may be a material such as Si, Siθ2, quartz, glass, or polyimide . The dielectric layer 406 may be an oxide or nitride material such as Siθ2 or SiN. However, the array 400 is not necessarily limited to the above-mentioned materials. These materials are mentioned as materials that can be readily adapted to conventional IC fabrication processes.

Although the explanation above explains a case where the contact holes 408 have the sloped walls 410 , the contact

holes 408 are not limited to this. The contact holes 408 may not have the sloped walls 410.

Figs . 5A and 5B are plan and cross- sectional views, respectively, depicting a variation of the neural sensor array of Fig. 4. As seen in Fig. 5A, the substrate 402 is a chip with edges 500. Typically, the chip has an area in the range of 1 square millimeter (mm ² ) to 100 mm ² . The conductive layer is formed into electrodes 502 , probe pads 504 along the chip edges 500, and traces 506 connecting the electrodes 502 to the probe pads 504. Note: in this view the dielectric layer and IrO _x nanowires are invisible.

As seen in Fig. 5B, the contact holes in the dielectric layer 406 include the neural interface contact hole 408 overlying each electrode 502 and a probing pad contact hole 508 overlying and exposing regions 510 of each probing pad

504. An IrO _x nanowire probe interface 512 is grown from the exposed regions 510 of each probing pad. In other aspects not shown, the probing pad 504 is left exposed without any IrO _x nanowires grown from exposed region 510. The probing pad contact hole 508 typically has a diameter 514 in the range of 200 micrometers to 2 mm.

Figs. 6A and 6B are plan views depicting other variations of the neural sensor array of Fig. 4. The IrO _x nanowire neural interfaces form an array of neural interface clusters 600 in a center region of the substrate 402 , where each cluster

includes between 2 and 12 electrodes (neural interfaces) . As shown, each dot represents a neural interface, and all the neural interface clusters in these examples include 4 neural interfaces. Each cluster 600 has a cluster diameter in the range of 5 to 50 micrometers (μm) . The cluster diameter is the distance between the furthest neural interfaces in a cluster. Note: the cluster diameters and number of neural interfaces per cluster need not necessarily be uniform. As shown in Figs. 6A and 6B , the cluster diameters are approximately 10 μm. The number of clusters on the substrate is typically in the range between 2 and 100, and they can be arranged in a pattern such as a circle, rectangle, or a grid. There are 32 clusters in each of the examples shown in Figs. 6A and 6B. The cluster pattern of Fig. 6A may be referred to as a circular pattern, while the pattern of Fig.

6A is rectangular.

The distance between clusters on the substrate may be uniform or varied, and may be measured from the substrate center or from adjacent clusters. In Fig. 6A, the distance between clusters may be measured as a function of the relative position of the cluster from the substrate center. In the first "ring" of clusters, the distance from center is approximately 25 μm, in the second ring the distance is 50 μm, in the third ring the distance is 75 μm, and in the fourth ring the distance is 100 μm. In Fig. 6B, the distance between

adjacent clusters is 50 μm. Functional Description

Figs. 7A through 7E are partial cross-sectional views depicting steps in the fabrication of an IrO _x nanowire neural sensor. A substrate 402 is provided, as shown in Fig. 7A. A conductive layer 404 such as Pt, Au, TiN or ITO is deposited on Si, Siθ2, quartz, or plastic wafers (substrate 402) (see Fig. 7B) . If ITO is used, an optional annealing process can be performed in oxygen at 200-600° C for 10 to 3600 seconds to improve the transparency of the ITO film. Then, the conductive layer 404 is patterned using a wet or dry etching process. In case of ITO, wet etching may be performed using an HCl based solution. After patterning the conductive layer 404 , a dielectric layer 406 such as Siθ2 or SiN is deposited on the wafer to passivate the conductive lines.

In Fig. 7C , contact holes 408 to the conductive layer 404 are etched out using either dry or wet etching process. In case of Siθ2 or undensified SiN dielectric, an HF based solution can be used to open up the contact holes 408. After etching, the wafer is transferred to Irθ2 chamber to grow Irθ2 or IrO _x nanowires, see Fig. 7D . Normally, the Irθ2 (IrO _x ) nanowires are grown on both the exposed conductive surface and also on dielectric surface.

In Fig. 7E, a second wet etching process is used to stripe the field Irθ2 nanowires (on the dielectric) , leaving the Irθ2

nanowires in the contact holes 408 in place. If Siθ2 or undensified SiN is used, an HF based solution also works well to stripe the field Irθ2 nanowires. In this second etching step, the dielectric layer 406 is partially striped away, leaving a sufficient thickness to passivate the conductive layer 404.

Fig. 7E depicts a neural interface 414 and a probe interface 512 connected by a conductive layer trace. Note: the figure is not drawn to scale .

One advantages of using a nanowire in a neural interface is that such as array can provide multiple electrical contacts at the cellular level, for electronically discriminating amongst individual cells or small groups of cells within a tissue or organ. Such an array can direct electrical signals to or from individual cells, or small groups of cells within such tissue or organ, especially neural tissues and organs. Neurologists have long sought electrode devices that can establish stable electrical contact with a large number of individual nerve fibers within a nerve. The ideal electrode device can be adapted to the anatomy of the nerve so that it can penetrate the nerve in a nondestructive fashion, in order to form focused individual electrical contacts with a very large number of individual nerve fibers. In order to make electrical contact with individual nerve fibers within a nerve, the use of a nanowire array is a good design choice. Irθ2 and IrO _x nanostructures have been successfully

grown on Si, polysilicon, glass, and ITO-coated polyimide flexible substrates, to name a few materials. Selective deposition can be obtained using refractory metal nano- particles, such as Ti, Ni, Au, etc. The growth length, density, and vertical orientation can be controlled by temperature, pressure, flow, substrates, and time.

Fig. 8 is a flowchart illustrating a method forming an IrO _x nanowire neural sensor array. Although the method is depicted as a sequence of numbered steps for clarity, the numbering does not necessarily dictate the order of the steps.

It should be understood that some of these steps may be skipped, performed in parallel, or performed without the requirement of maintaining a strict order of sequence. The method starts at Step 800. Step 802 provides a substrate such as Si, Siθ2, quartz, glass, or polyimide. Step 804 forms a conductive layer overlying the substrate, from a material such as ITO, SnO ₂ , ZnO, TiO2, doped ITO, doped Snθ2, doped ZnO, doped TiO ₂ , TiN, TaN, Au, Pt, or Ir. Step 806 forms a dielectric layer overlying the conductive layer from an oxide or nitride material such as SiO ₂ and SiN. Step 808 selectively wet etches the dielectric layer. Step 8 10 forms contact holes with sloped walls in the dielectric layer, exposing regions of the conductive layer. Step 812 grows IrO _x nanowire neural interfaces from the exposed regions of the conductive layer.

Although the explanation above explains a case where contact holes with sloped walls are formed, the contact holes are not limited to this. The contact holes may not have sloped walls. When growing IrO _x nanowires from a small hole, a shadowing effect associated with the hole or via walls inhibits the growth of the nanowires. Therefore, a wet etching process is used which forms a sloped, as opposed to vertical wall structure, where the narrow aperture of the hole is adjacent (overlying) the conductive layer. Since the wall of the contact hole is sloped, the shadowing effect is reduced, enabling the growth of nanowires in aperture diameters as small as 0.5 um. Typically, the growth of the IrO _x nanowire neural interface in Step 812 includes forming each neural interface with a cross- section in the range of 0.5 to 10 micrometers, with a shape such as a circle, rectangle, or oval.

In another aspect, growing IrO _x nanowire neural interfaces in Step 8 12 includes substeps. Step 812a grows IrO _x nanowires from the exposed regions of conductive layer and from a top surface of the dielectric layer. Step 812b selectively etches the dielectric layer, and Step 812c removes the IrO _x nanowires from the dielectric layer top surface.

In one aspect, providing the substrate in Step 802 includes providing a substrate chip with edges. Then prior to forming the dielectric layer in Step 806, Step 805 etches the

conductive layer to form electrodes, probe pads along the chip edges, and traces connecting the electrodes to the probe pads. Forming contact holes in the dielectric layer in Step 810 includes forming a neural interface contact hole overlying each electrode and a probing pad contact hole overlying and exposing regions of each probing pad. Step 8 12 may additionally grow IrO _x nanowires from the exposed regions of the probing pads .

In another aspect, Step 802 provides a substrate chip having an area in the range of 1 mm ² to 100 mm ² . Etching the conductive layer to form electrodes in Step 805 includes forming an array of electrode clusters in a center region of the substrate, where each cluster includes between 2 and 12 electrodes . Each cluster has a diameter in the range of 5 to 50 micrometers. The number of clusters on a chip is in the range of 2 and 100, and the clusters are arranged in a pattern such as a circle , rectangle, or a grid.

Additional details of the IrO _x nanowire fabrication process can be found in the following related pending applications:

OPTICAL DEVICE WITH IrO _x NANOSTRUCTURE

ELECTRODE NEURAL INTERFACE, invented by Zhang et al,

Serial No. 1 1 /496, 157, filed July 31 , 2006, Attorney Docket

No. SLA8084; IRIDIUM OXIDE NANOTUBES AND METHOD FOR

FORMING SAME, invented by Zhang et al., Serial No. 10/971,280, filed October 21, 2004, Attorney Docket No. SLA0901 (US patent No.7,098,144); and,

IRIDIUM OXIDE NANOWIRE AND METHOD FOR FORMING SAME, invented by Zhang et al., Serial No.

10/971,330, filed October 21, 2004, Attorney Docket No. SLA0903 (US patent No. 7,255,745). The three above- mentioned applications are incorporated herein by reference. An IrO _x nanowire neural sensor array and corresponding fabrication processes have been provided. Examples of specific materials, process steps, and structures have been presented to illustrate the invention. However, the invention is not limited to merely these examples. Other variations and embodiments of the invention will occur to those skilled in the art.