ORTHOGONAL TIME FREQUENCY SPACE MODULATED SIGNALS

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent document claims priority to U.S. Provisional Application Serial No. 62/317,420, entitled "ITERATIVE TWO DIMENSIONAL EQUALIZATION OF

ORTHOGONAL TIME FREQUENCY SPACE MODULATED SIGNALS," filed on April 1, 2016. The entire content of the aforementioned patent application is incorporated by reference herein.

TECHNICAL FIELD

[0002] The present document relates to wireless communication, and more particularly, to receiver-side processing of orthogonal time frequency space (OTFS) domain modulated signals.

BACKGROUND

[0003] Due to an explosive growth in the number of wireless user devices and the amount of wireless data that these devices can generate or consume, current wireless communication networks are fast running out of bandwidth to accommodate such a high growth in data traffic and provide high quality of service to users.

[0004] Various efforts are underway in the telecommunication industry to come up with next generation of wireless technologies that can keep up with the demand on performance of wireless devices and networks.

SUMMARY

[0005] This document discloses receiver-side techniques for iterative two-dimensional channel equalizer in which input time-frequency domain train of symbols and channel estimates are, in a feed forward path, transformed into delay -Doppler domain and data bits are extracted in the delay -Doppler domain. In the feedback path, the data bit estimates are transformed using a symplectic Fourier transform into time-frequency domain to generate symbol estimates for the next iteration.

[0006] In one example aspect, a wireless communication method for recovering information bits from a received signal, by performing iterative two dimensional equalization is disclosed. The method includes receiving, at an iterative equalizer, iteration inputs including a two dimensional estimate of a wireless channel over which the received signal is received, a stream of received symbols, a symbol estimate from a previous iteration, an input autocorrelation matrix estimate from the previous iteration, computing, from the iteration inputs, a Wiener estimate of the stream of received symbols, transforming the Wiener estimate to symbol estimates a two dimensional delay-Doppler grid using a two-dimensional symplectic Fourier transform, estimating likelihoods of the symbol estimates in the two dimensional delay-Doppler grid, and generating estimates of data from the likelihoods.

[0007] In another example aspect, a wireless communication method for recovering information bits from a received signal, by performing iterative two dimensional equalization is disclosed. The method includes receiving, at an iterative equalizer, iteration inputs including a two dimensional estimate of a wireless channel over which the received signal is received, a stream of received symbols, a symbol estimate from a previous iteration, an input autocorrelation matrix estimate from the previous iteration, computing, from the iteration inputs, a Wiener estimate of the stream of received symbols, transforming the Wiener estimate to symbol estimates a two dimensional delay-Doppler grid using a two-dimensional symplectic Fourier transform, and processing in a feedback direction, by generating a symbol estimate and an input autocorrelation matrix estimate for a next iteration.

[0008] These, and other, features are described in this document.

DESCRIPTION OF THE DRAWINGS

[0009] Drawings described herein are used to provide a further understanding and constitute a part of this application. Example embodiments and illustrations thereof are used to explain the technology rather than limiting its scope.

[0010] FIG. 1 shows an example communication network.

[0011] FIG. 2 shows a flowchart of an example wireless communication reception method.

[0012] FIG. 3 shows a flowchart of another example wireless communication reception method.

[0013] FIG. 4 shows an example of a wireless transceiver apparatus.

[0014] FIG. 5 is a block diagram showing an example 2-D iterative equalizer.

[0015] FIG. 6 is a block diagram showing an example of a self-iterative 2-D equalizer. DETAILED DESCRIPTION

[0016] To make the purposes, technical solutions and advantages of this disclosure more apparent, various embodiments are described in detail below with reference to the drawings. Unless otherwise noted, embodiments and features in embodiments of the present document may be combined with each other.

[0017] The present-day wireless technologies are expected to fall short in meeting the rising demand in wireless communications. Many industry organizations have started the efforts to standardize next generation of wireless signal interoperability standards. The 5th Generation (5G) effort by the 3rd Generation Partnership Project (3GPP) is one such example and is used throughout the document for the sake of explanation. The disclosed technique could be, however, used in other wireless networks and systems.

[0018] Section headings are used in the present document, including the appendices, to improve readability of the description and do not in any way limit the discussion to the respective sections only.

[0019] FIG. 1 shows an example communication network 100 in which the disclosed technologies can be implemented. The network 100 may include a base station transmitter that transmits wireless signals s(t) (downlink signals) to one or more receivers 102, the received signal being denoted as r(t), which may be located in a variety of locations, including inside or outside a building and in a moving vehicle. The receivers may transmit uplink transmissions to the base station, typically located near the wireless transmitter. The technology described herein may be implemented at a receiver 102, or in the base station.

[0020] A 2-D equalizer may be used to extract data bits that are modulated on symbols received via OTFS modulation.

[0021] 1. Introduction

[0022] A system with N transmit antennas and M receives antennas, is used to pass information over a multipath channel. Information bits, b, are encoded into coded bits, c, using an Forward Error Correction (FEC) code (such as convolutional code, turbo code or LDPC code). These coded bits are grouped into groups of q bits, optionally interleaved and mapped to symbols x in a finite constellation Ω (such as 2 ^q — QAM) multiplexed on a grid on the 2-D Delay Doppler grid. These symbols are transformed by a 2-D Inverse Symplectic Fourier transform to symbols X multiplexed on a reciprocal grid on the time frequency plane. These symbols are OFDM modulated and transmitted over the N antennas. The signal, received in M antennas, is OFDM demodulated and processed as a 2-D Time-Frequency grid in the receiver.

In the 2-D Time-Frequency grid, the channel equation can be written individually for each symbol (or time-frequency point) indexed by as

v&i — H&i) . C'- ⁾ M/C'- ) ( 1 ) zMxl ^~ "MxN ^Λ «Χ1 ^{T κ} Μχ1

[0023] where W^x _i ^re P ^resen t a vector of AWGN samples with expectation zero and variance R _w . The 2-D equalizer computes estimations of the transmitted symbols x from the received samples Y, the channel estimations H and the noise variance R _w . In a non-iterative receiver, the estimated samples are transformed to the Delay-Doppler domain via a 2-D Symplectic Fourier transform and then converted to bit likelihoods, which are passed to FEC decoder to generate estimates, b, on the information bits.

[0024] 2. Iterative 2-D Equalizer

[0025] FIG. 5 is a block diagram of an example embodiment of an iterative 2-D equalizer 501. The 2-D Iterative equalizer, illustrated in FIG. 5, iterates between the 2-D equalizer 503 and the FEC MAP decoder 505, by passing information from one to the other. After several iterations, the MAP decoder outputs estimation on the information bits. In various embodiments, the iteration termination criteria may be based on a total number of iterations, meeting, but not exceeding, a time budget for the iterative process, the

improvement in successive iterations falling below a threshold, and so on.

[0026] 2.1 Example embodiments of the 2-D Equalizer (503)

[0027] In some embodiments, the 2-D equalizer may be implemented as an affine MMSE equalizer, computing the Wiener estimator of X

X = CY + (/ - CH)X (2)

[0028] where C = RxyRy ¹ and / is the identity matrix. Note that C is a function of R _x and R _w . For the first iteration there is no prior information on the symbols of X, therefore we set X = 0 and R _x = I. The 2-D equalizer also computes the variance of the estimation error, denoted as R _E .

[0029] 2.2 2-D SFFT (507)

[0030] The estimated symbols and error variances, X and R _E respectively, are transformed from the 2-D Time-Frequency grid to the 2-D Delay-Doppler grid via a 2-D Symplectic Fourier transform to x and R _e respectively.

[0031] 2.3 Likelihoods (509) [0032] Likelihoods for the coded bits L _E (x), are computed from the symbols x.

Gaussian distribution may be assumed for x and the likelihoods can be derived from it. The probabilities for this case are

-ϊ -(χ-μ(ω,Α)) ² (3) P(x \x = ω) oc e ^R z

[0033] where ωεΩ. is a constellation symbol and

A = 1 - ReRx ¹ (4)

R _z = AR _e

μ(ω, A) = ωΑ + (1 - A)x

[0034] Note that x is defined in equation (7). For each symbols, the extrinsic coded bits log likelihoods ratio (LLR) can be derived as

[0035] where i, = 0, ... , q— 1, χ(ω) is the constellation bits label that is associated with the constellation symbol ω and (ω) ₇ is defined in equation (6).

[0036] 2.4 Deinterleaver (51 1)

[0037] The deinterleaver permutes the likelihoods L _E (x) to L(C) . These likelihoods will be used as a priori information for the MAP decoder. In some implementations this deinterleaver might be optional.

[0038] 2.5 MAP Decoder (505)

[0039] The Maximum A Posteriori decoder computes the a posteriori probabilities (APP's) of the information bits and also the extrinsic probabilities for the coded bits, which when using LLRs, are the APP's minus the a priori inputs.

[0040] 2.6 Interleaver (513)

[0041] The interleaver permutes the likelihoods L _D (C) to L(x) . These likelihoods will be used as a priori information for the MAP decoder. Note that in some implementations this interleaver might be optional.

[0042] 2.7 Symbol Mapper (515)

[0043] The symbol mapper estimates the probabilities of each constellation symbol ωεΩ. from the likelihoods values L(x) :

[0044] These probabilities are used for computing the expectation of the constellation and the variance:

q-1 (7)

X = ω ^■ Ρ(ω)

ί=0

[0045] 2.8 2-D SFFT (517)

[0046] The 2-D Delay-Doppler domain symbols' expectation and variance x and R _x are transformed to X and R _x in the 2-D Time-Frequency domain using a 2-D Inverse Symplectic Fourier transform to transform from the delay -Doppler domain to the Time-Frequency domain. These are used as priors to the 2-D Equalizer in the next iteration. In some embodiments, the 2-D transforms used by operation 507 and 517 may be swapped. In other words, an inverse SFFT may be used in the operation 507, while an SFFT may be used in the operation 517.

[0047] In some embodiments, the iterative 2-D Equalizer may be operated so that the receiver gets side information about some resource elements in the time-frequency grid that have been "erased" (e.g., not transmitted, or not useable) and the receiver can ignore them. The receiver may skip equalization for these resources and just uses directly the prior estimates as outputs for the equalizer. In this case, Eq (2) simply becomes for these resources^ = X.

[0048] 3. Self-Iterative 2-D Equalizer (600)

[0049] In the scheme 600, shown in FIG. 6, the 2-D equalizer 503 generates symbols estimations x and R _e in the 2-D Delay-Doppler domain in a similar way to the one described in the previous section. However, these estimates are fed directly to the soft symbol mapper 615 to generate along with 2-D inverse Symplectic Fourier transform 517, new priors for the 2-D equalizer 503. After a number of iterations, with termination criteria described as before, these estimations are converted to coded bits likelihoods and passed to the FEC decoder 605 to generate estimation of the information bits.

[0050] As depicted in the flowchart of FIG. 2, a wireless communication method 200 for recovering information bits from a received signal, by performing iterative two

dimensional equalization includes receiving (202), at an iterative equalizer, iteration inputs including a two dimensional estimate of a wireless channel over which the received signal is received, a stream of received symbols, a symbol estimate from a previous iteration, an input autocorrelation matrix estimate from the previous iteration, computing (204), from the iteration inputs, a Wiener estimate of the stream of received symbols, transforming (206) the Wiener estimate to symbol estimates a two dimensional delay-Doppler grid using a two- dimensional symplectic Fourier transform, which may be a fast SFFT or a fast SFFT ^"1 , estimating (208) likelihoods of the symbol estimates in the two dimensional delay-Doppler grid, and generating (210) estimates of data from the likelihoods. Various embodiments and options are further described in the description associated with FIG. 5. For example, as described with respect to operations 507 and 517, in some embodiments, two-dimensional symplectic Fourier transforms that are inverse of each other may be used in these operations. In other words, 507 may correspond to an SFFT while 517 may correspond to an inverse SFFT or vice versa.

[0051] In some embodiments the generating the estimate may include deinterleaving the likelihoods and performing error correction. As depicted in the example embodiment in FIG. 5, in some embodiments, the feedback direction processing may include generating a symbol estimate and an input autocorrelation matrix estimate for a next iteration of the method 200. The processing in the feedback direction may include performing soft symbol mapping using the likelihoods resulting in intermediate symbol estimates and an intermediate autocorrelation estimate, and generating the symbol estimate and the input autocorrelation matrix estimate by transforming, using an inverse of the two-dimensional symplectic Fourier transform, the intermediate symbol estimates and the intermediate autocorrelation estimate. In various embodiments, the two-dimensional symplectic Fourier transform may be SFFT or SFFT ^"1 .

[0052] In some embodiments, the receiver that implements the method 200 may get side information about some resource elements in the time-frequency grid that have been "erased" (not transmitted, or not useable) and the receiver can ignore them. The receiver may then skip the equalization for them and just uses directly the prior estimates as outputs for the equalizer. In this case, Eq (2) simply becomes for these resources X = X. [0053] FIG. 3 illustrates a flowchart example for a wireless communication method 300 for recovering information bits from a received signal, by performing iterative two dimensional equalization is disclosed. The method 300 includes receiving (302), at an iterative equalizer, iteration inputs including a two dimensional estimate of a wireless channel over which the received signal is received, a stream of received symbols, a symbol estimate from a previous iteration, an input autocorrelation matrix estimate from the previous iteration, computing (304), from the iteration inputs, a Wiener estimate of the stream of received symbols, transforming (306) the Wiener estimate to symbol estimates a two dimensional delay-Doppler grid using a two-dimensional symplectic Fourier transform, and processing (308) in a feedback direction, by generating a symbol estimate and an input autocorrelation matrix estimate for a next iteration. Various embodiments and options are further described in the description associated with FIG. 6.

[0054] FIG. 4 shows an example of a wireless transceiver apparatus 500. The apparatus 500 may be used to implement method 200 or 300. The apparatus 500 includes a processor 502, a memory 504 that stores processor-executable instructions and data during

computations performed by the processor. The apparatus 500 includes reception and/or transmission circuitry 506, e.g., including radio frequency operations for receiving or transmitting signals.

[0055] It will be appreciated that techniques for wireless data reception are disclosed by performing iterative 2D channel equalization in the delay-Doppler domain.

[0056] The disclosed and other embodiments, modules and the functional operations described in this document can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this document and their structural equivalents, or in combinations of one or more of them. The disclosed and other embodiments can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more them. The term "data processing apparatus" encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them. A propagated signal is an artificially generated signal, e.g., a machine- generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus.

[0057] A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.

[0058] The processes and logic flows described in this document can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0059] Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0060] While this patent document contains many specifics, these should not be construed as limitations on the scope of an invention that is claimed or of what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features that are described in this document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or a variation of a sub-combination. Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results.

[0061] Only a few examples and implementations are disclosed. Variations, modifications, and enhancements to the described examples and implementations and other implementations can be made based on what is disclosed.