JUNCTION FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR

WIPO Patent Application WO/2016/000600

A1

The present invention relates to a junction field effect transistor. The junction field effect transistor comprises a substrate (10), a buried layer in the substrate, a first well region (32) and a second well region (34) that are on the buried layer, a source lead-out region (50), a drain lead-out region (60), and a first gate lead-out region (42) that are in the first well region (32), and a second gate lead-out region (44) in the second well region (34). A Schottky junction interface (70) is disposed on the surface of the first well region (32). The Schottky junction interface (70) is located between the first gate lead-out region (42) and the drain lead-out region (60), and is isolated from the first gate lead-out region (42) and the drain lead-out region (60) by means of isolation structures. The present invention also relates to a manufacturing method for a junction field effect transistor.

JP3842842	SEMICONDUCTOR CRYSTAL BODY AND PRODUCTION THEREOF, SEMICONDUCTOR LASER AND FABRICATION THEREOF, SEMICONDUCTOR LIGHT RECEIVING ELEMENT AND FABRICATION THEREOF, AND FIELD EFFECT TRANSISTOR AND FABRICATION THEREOF
JP7126082	Crystalline oxide semiconductor film and semiconductor device
JP3363561	Description: JFETN field effect transistor

HAN GUANGTAO (CN)
SUN GUIPENG (CN)

PCT/CN2015/082761

January 07, 2016

June 30, 2015

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CSMC TECHNOLOGIES FAB1 CO LTD (CN)

H01L29/808; H01L21/337

CN103178093A	2013-06-26
US20140061731A1	2014-03-06
CN101350351A	2009-01-21
CN102842596A	2012-12-26
CN103296082A	2013-09-11

ADVANCE CHINA IP LAW OFFICE (CN)
广州华进联合专利商标代理有限公司 (CN)

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