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Title:
LADDER CIRCUIT EDITING DEVICE
Document Type and Number:
WIPO Patent Application WO/2000/007081
Kind Code:
A1
Abstract:
A ladder circuit editing device provided with an inputted region which receives and edits a sequence program of a program controller in the form of a ladder diagram and is stored with at least one circuit pattern that has been received, and an uninputted region where a new circuit pattern is to be inputted and which successively receives circuit patterns from the inputted region, the inputted region comprising a circuit pattern extracting means which compares constituent elements of a circuit pattern that is being inputted into the uninputted region with constituent elements of a circuit pattern stored in the inputted region and extracts circuit patterns including constituent elements that are in agreement, a means for displaying the extracted circuit patterns on an input screen, and a means for copying the extracted circuit patterns on the uninputted region according to the input of operation.

Inventors:
IWATA YASUNOBU (JP)
WATANABE TAKU (JP)
YAMADA SHIGEKI (JP)
KIMURA HIROYASU (JP)
HARADA TERUYUKI (JP)
NAKAMURA TOMOKO (JP)
Application Number:
PCT/JP1998/003402
Publication Date:
February 10, 2000
Filing Date:
July 30, 1998
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP (JP)
IWATA YASUNOBU (JP)
WATANABE TAKU (JP)
YAMADA SHIGEKI (JP)
KIMURA HIROYASU (JP)
HARADA TERUYUKI (JP)
NAKAMURA TOMOKO (JP)
International Classes:
G05B19/05; (IPC1-7): G05B19/05
Foreign References:
JPH02220102A1990-09-03
JPH07146642A1995-06-06
JPH07319513A1995-12-08
JPH09251305A1997-09-22
JPH05189012A1993-07-30
JPH0695712A1994-04-08
JPH04348404A1992-12-03
JPH04205312A1992-07-27
JPS6255703A1987-03-11
JPH0310322A1991-01-17
Attorney, Agent or Firm:
Soga, Michiteru (8th floor 1-1, Marunouchi 3-chome Chiyoda-ku Tokyo, JP)
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