Title:
LAMINATE MOLDING METHOD USING HIGH-PURITY SILICON, LAMINATE MOLDING METHOD FOR SEMICONDUCTOR PRODUCTION DEVICE COMPONENT, SEMICONDUCTOR PRODUCTION DEVICE COMPONENT, AND METHOD FOR FORMING SEMICONDUCTOR PRODUCTION DEVICE COMPONENT
Document Type and Number:
WIPO Patent Application WO/2024/029329
Kind Code:
A1
Abstract:
This laminate molding method uses high-purity silicon, and comprises: a step for setting a vacuum treatment container in a high vacuum state; a step for heating a base plate provided in the vacuum treatment container; a step for depositing silicon powder on the base plate; a step for forming a molten silicon layer by scanning the base plate with a molding energy ray to form a molten silicon layer; and a step for cooling the molten silicon layer to form a solidified silicon layer. In the method, a cycle including the step for depositing the silicon powder, the step for forming the molten silicon layer, and the step for forming the solidified silicon layer is repeatedly performed.
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Inventors:
ISHII TAKAYUKI (JP)
SAITO MICHISHIGE (JP)
NAGASEKI KAZUYA (JP)
CHIBA AKIHIKO (JP)
AOYAGI KENTA (JP)
WANG HAO (JP)
SAITO MICHISHIGE (JP)
NAGASEKI KAZUYA (JP)
CHIBA AKIHIKO (JP)
AOYAGI KENTA (JP)
WANG HAO (JP)
Application Number:
PCT/JP2023/026319
Publication Date:
February 08, 2024
Filing Date:
July 18, 2023
Export Citation:
Assignee:
TOKYO ELECTRON LTD (JP)
International Classes:
H01L21/3065; H01L21/205; H05H1/46
Domestic Patent References:
| WO2021041110A1 | 2021-03-04 |
Foreign References:
| JP2021197457A | 2021-12-27 | |||
| JPH076970A | 1995-01-10 | |||
| JP2021063273A | 2021-04-22 | |||
| JP2009054984A | 2009-03-12 | |||
| JPH0547678A | 1993-02-26 | |||
| JPS5461888A | 1979-05-18 |
Attorney, Agent or Firm:
KANEMOTO, Tetsuo et al. (JP)
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