Title:
LAMINATION OF HIGH-LAYER-COUNT SUBSTRATES
Document Type and Number:
WIPO Patent Application WO2003078153
Kind Code:
A3
Abstract:
The present invention provides a number of techniques for laminating and interconnecting multiple high-layer-count "HLC" substrates (100) to form a multilayer package or other circuit component. A solder bump (154) may be formed on the conductive pad (134) of at least one of two HLC substrates (164, 166). The solder bump (154) preferably is formed from an application of solder paste (144) to the conductive pad(s) (134). An adhesive film (160) may be positioned between the surfaces of the HLC substrates (164, 166) having the conductive pads (134), where the adhesive film (160) includes an aperture (162) located substantially over the conductive pads (134) such that the conductive pads (134) and/or solder bumps (154) confront each other through the aperture (162). The HLC substrates (100) then may be pressed together to mechanically bond the two substrates via the adhesive (160). The solder bump(s) (154) may be reflowed during or after the lamination to create a solder segment (170) that provides an electrical connection between the two conductive pads (134) through the aperture (162) in the adhesive film (160).
Inventors:
PAI DEEPAK K
DENNY RONALD R
DENNY RONALD R
Application Number:
PCT/US2003/007842
Publication Date:
December 18, 2003
Filing Date:
March 14, 2003
Export Citation:
Assignee:
GEN DYNAMICS ADVANCED INF SYS (US)
International Classes:
H05K1/14; H01L23/12; H05K3/36; H05K3/46; H05K3/28; H05K3/34; (IPC1-7): H05K1/02; H01R12/16; H05K1/11
Foreign References:
| US6320140B1 | 2001-11-20 | |||
| US5977490A | 1999-11-02 | |||
| US6139777A | 2000-10-31 |
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