Title:
LATENCY-DRIVEN DATA ACTIVITY SCHEME FOR LAYER 2 POWER OPTIMIZATION
Document Type and Number:
WIPO Patent Application WO/2023/282888
Kind Code:
A8
Abstract:
According to one aspect of the present disclosure, a baseband chip including a downlink (DL) Layer 2 block is disclosed. The DL Layer 2 block may include a buffer configured to receive a DL Layer 2 protocol data unit (PDU) from a Medium Access Control (MAC) circuit. The DL Layer 2 block may also include a microcontroller. The microcontroller may be configured to determine whether a DL Layer 2 processing circuit is active. The microcontroller may be further configured to delay an activation of the DL Layer 2 processing circuit until a trigger event occurs when it is determined that the DL Layer 2 processing circuit is inactive. The DL Layer 2 block may further include a DL Layer 2 processing circuit. The DL Layer 2 processing circuit may be configured to fetch the PDU from the buffer when activated. The DL Layer 2 processing circuit may be further configured to perform Layer 2 processing of the PDU.
Inventors:
LOW SU-LIN (US)
LI YUNHONG (US)
HONG HAUSTING (US)
LEE CHUN-I (US)
KOVOOR SHEETHAL (US)
MA TIANAN (US)
LI JIANZHOU (US)
BAGCHI SONALI (US)
PAO SAMMY TZU-KIANG (US)
CHEN NA (US)
KI SANGWON (US)
WANG ZENGYU (US)
SURESHCHANDRAN SWAMINATHAN (US)
WEE SUN HEE (US)
LI YUNHONG (US)
HONG HAUSTING (US)
LEE CHUN-I (US)
KOVOOR SHEETHAL (US)
MA TIANAN (US)
LI JIANZHOU (US)
BAGCHI SONALI (US)
PAO SAMMY TZU-KIANG (US)
CHEN NA (US)
KI SANGWON (US)
WANG ZENGYU (US)
SURESHCHANDRAN SWAMINATHAN (US)
WEE SUN HEE (US)
Application Number:
PCT/US2021/040496
Publication Date:
April 27, 2023
Filing Date:
July 06, 2021
Export Citation:
Assignee:
ZEKU INC (US)
International Classes:
H04W72/04; H04W72/12
Attorney, Agent or Firm:
ZOU, Zhiwei (US)
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