Title:
LAYERED CERAMIC ELECTRONIC COMPONENT MOUNTING STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2024/047973
Kind Code:
A1
Abstract:
Provided is a layered ceramic electronic component mounting structure that suppresses a reduction in the stability of a mounting posture. A mounting structure 90 is a mounting structure in which a layered ceramic electronic component 1 is mounted on a circuit board CB. The layered ceramic electronic component 1 comprises: a layered body in which an inner conductor layer and a plurality of dielectric layers made of a ceramic material are layered; and a first outer electrode 41 and a second outer electrode 42 disposed on only two principal surfaces or on only one principal surface of the layered body. The circuit board CB comprises a first land electrode 51 and a second land electrode 52. An inside end of the first outer electrode 41 is positioned more toward the second outer electrode 42 side and the second land electrode 52 side than an inside end of the first land electrode 51, and an inside end of the second outer electrode 42 is positioned more toward the first outer electrode 41 side and the first land electrode 51 side than an inside end of the second land electrode 52.
Inventors:
HARADA TOSHIHIRO (JP)
Application Number:
PCT/JP2023/019377
Publication Date:
March 07, 2024
Filing Date:
May 24, 2023
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H01G2/06; H01G4/30
Foreign References:
| JP2007129224A | 2007-05-24 | |||
| JPH09139324A | 1997-05-27 | |||
| JP2014011210A | 2014-01-20 | |||
| JP2019134067A | 2019-08-08 |
Attorney, Agent or Firm:
KATO Ryuta et al. (JP)
Download PDF:
Previous Patent: INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD
Next Patent: FREQUENCY RESPONSE FUNCTION IDENTIFICATION SYSTEM
Next Patent: FREQUENCY RESPONSE FUNCTION IDENTIFICATION SYSTEM