Title:
LAYERED STRUCTURE, MANUFACTURING METHOD THEREFOR, AND SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/048005
Kind Code:
A1
Abstract:
This layered structure comprises: an amorphous substrate that has an insulating surface; an orientation layer that has a pattern on the amorphous substrate having the insulating surface; a semiconductor layer that contains a gallium nitride and has a pattern disposed on the upper surface of the orientation layer; and a side-surface protection part that contains a gallium nitride and is disposed on a side surface of the orientation layer, the semiconductor layer and the side-surface protection part being spaced apart from each other on the side surface of the orientation layer. A first angle formed by the bottom surface and the side surface of the orientation layer may be 60°-90°. Furthermore, the semiconductor layer contains a gallium nitride having the same composition as the side-surface protection part. The crystallinity of the gallium nitride of the semiconductor layer may be higher than the crystallinity of the gallium nitride of the side-surface protection part.
Inventors:
AOKI HAYATA (JP)
NISHIMURA MASUMI (JP)
NISHIMURA MASUMI (JP)
Application Number:
PCT/JP2023/021906
Publication Date:
March 07, 2024
Filing Date:
June 13, 2023
Export Citation:
Assignee:
JAPAN DISPLAY INC (JP)
International Classes:
H01L21/20
Foreign References:
| JP2012119569A | 2012-06-21 | |||
| JP2012076984A | 2012-04-19 | |||
| JP2000269605A | 2000-09-29 | |||
| JP2018030766A | 2018-03-01 |
Attorney, Agent or Firm:
TAKAHASHI, HAYASHI AND PARTNER PATENT ATTORNEYS, INC. (JP)
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