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Title:
LED VERTICAL CHIP STRUCTURE WITH SPECIAL COARSENING MORPHOLOGY AND PREPARATION METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2016/041471
Kind Code:
A1
Abstract:
A method for improving luminous efficiency of an LED in a vertical structure. First, an LED vertical chip structure with a special coarsening morphology is provided, and micron-scale holes (311) are formed in the surface of an epitaxial structure layer (300) and submicron-scale holes (312) are formed at the bottom of the micron-scale holes. The light emitting surface structure can increase the emission probability of light inside a device, and can greatly improve the light emission efficiency. Also provided is a preparation method for the chip structure. Micron-scale holes (311) are formed in an epitaxial structure layer (300) by stripping a growth substrate (100) with micron-scale bumps, and submicron-scale holes (312) are formed at the bottom of the micron-scale holes (311) by means of etching. The method is simple in process, can be applied to large-scale industrial production, and can greatly improve the luminous efficiency of the LED in the vertical structure.

Inventors:
TONG LING (CN)
ZHANG QIONG (CN)
LV MENGYAN (CN)
ZHANG YU (CN)
LI QIMING (CN)
Application Number:
PCT/CN2015/089497
Publication Date:
March 24, 2016
Filing Date:
September 14, 2015
Export Citation:
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Assignee:
ENRAYTEK OPTOELECTRONICS CO (CN)
International Classes:
H01L33/22; H01L33/00
Foreign References:
CN104218134A2014-12-17
CN103022301A2013-04-03
CN101071840A2007-11-14
CN203434183U2014-02-12
CN101740689A2010-06-16
Attorney, Agent or Firm:
SHANGHAI SAVVY INTELLECTUAL PROPERTY AGENCY (CN)
上海思微知识产权代理事务所（普通合伙） (CN)
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