Title:
LEVEL SHIFTER CIRCUIT, DRIVE CIRCUIT, AND DISPLAY
Document Type and Number:
WIPO Patent Application WO/2006/040904
Kind Code:
A1
Abstract:
A level shifter control circuit (10) generates a control signal (ENB1) for controlling level shift operation of a level shifter (LS1) depending on the input timing of output signals (Sx and Sy) from a source shift register (20). Signals having a mutual input interval shorter than the active period of a clock signal (GCK1) are employed as the output signals (Sx and Sy) from the source shift register (20). When stopping the level shift operation, the level shifter (LS1) holds an output signal (OUT1) in the state before stopping the level shift operation. Consequently, power consumption of the level shifter circuit can be reduced.
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Inventors:
MATSUDA EIJI
YOKOYAMA MAKOTO
MURAKAMI YUHICHIROU
YOKOYAMA MAKOTO
MURAKAMI YUHICHIROU
Application Number:
PCT/JP2005/017141
Publication Date:
April 20, 2006
Filing Date:
September 16, 2005
Export Citation:
Assignee:
SHARP KK (JP)
MATSUDA EIJI
YOKOYAMA MAKOTO
MURAKAMI YUHICHIROU
MATSUDA EIJI
YOKOYAMA MAKOTO
MURAKAMI YUHICHIROU
International Classes:
H03K19/0175; G02F1/133; G09G3/20
Domestic Patent References:
| WO2003036606A1 | 2003-05-01 |
Foreign References:
| JPH0690161A | 1994-03-29 | |||
| JP2004005904A | 2004-01-08 | |||
| JP2004046085A | 2004-02-12 |
Attorney, Agent or Firm:
HARAKENZO WORLD PATENT & TRADEMARK (2-6Tenjinbashi 2-chome Kita, Kita-k, Osaka-shi Osaka 41, JP)
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