TECHNICAL FIELD

The invention relates to a switching arrangement, a system and a method for load transfer of supply voltage. BACKGROUND

Static transfer switches (STSs) are typically used in uninterruptable power supply (UPS) systems, both in low voltage (LV) and medium voltage (MV) applications.

A MV UPS system is illustrated in Fig. l. An STS (utility disconnect) is as illustrated in Fig. ι used to supply a load. The STS opens in case a utility supply fails in some way and disconnects the load and the three parallel energy delivery units (EDUs). The power supply to the load is now provided through the three EDUs instead of through the utility power supply. The system also comprises a mechanical, maintenance, bypass switch.

A typical STS operates when a disturbance in supply voltage is detected and responds by transferring a sensitive load to an alternative supply voltage.

A Fast mechanical Commutating Switch (FCS) cannot break current, but it can very quickly commutate current into another parallel circuit path, most often a fuse or a semiconductor device.

A fast acting mechanical breaker is in WO9811645 used in combination with a solid state switch to provide a hybrid breaker.

A fast mechanical commutating switch is disclosed in US 7235751, which describes an electric device including an electric switch having a plurality of contact members arranged in series to form a plurality of breaking points arranged in series. SUMMARY

An object of the present invention is how to improve the efficiency of load transfer during operation.

According to a first aspect, a switching arrangement for load transfer of supply voltage is presented. The switching arrangement comprises a static transfer switch (STS), and a fast mechanical commutating switch (FCS) connected in parallel with the STS, such that when both the FCS and the STS are closed a current loop there through is created.

The STS may be a forced commutating switch, such as an IGBT, an IGCT or a BIGT.

The STS may be a line commutated switch, such as a thyristor or an SCR.

The switching arrangement may be connected between a supply voltage and a load. The switching arrangement may comprise a second STS and a second FCS connected in parallel with the second STS, wherein the second STS and second FCS are connected between a second supply voltage and the load.

The switching arrangement may comprise a forced commutated switch connected in series with the FCS, such that the forced commutated switch and the FCS together are connected in parallel with the STS.

The switching arrangement may be configured for low, medium or high voltage applications.

According to a second aspect, a system for voltage supply of a load is presented. The system comprises a switching arrangement connected between a first supply voltage and a load, and a second switching

arrangement connected between a second supply voltage and the load. According to a third aspect, a method for load transfer of supply voltage is presented. The method comprises closing a static transfer switch (STS) connected to a first supply voltage and to a load, providing a closed current loop through the STS and a fast mechanical commutating switch (FCS) arranged in parallel with the STS, opening the FCS, closing a switch connected to the load and a second supply voltage, and opening the STS.

The step of closing a switch may be made after the FCS has been opened, commutation to the STS has been completed, and the STS has interrupted the current.

An advantage with a switching arrangement according to the present invention is that energy consumption is reduced during normal operation, and further removes the need of liquid or forced air cooling of an STS.

Further, improved availability for a load is at the same time achieved by reduced down time.

Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise herein. All references to "a/an/the element, apparatus, component, means, step, etc." are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is now described, by way of example, with reference to the accompanying drawings, in which:

Fig. 1 schematically illustrates a UPS system;

Fig. 2 schematically illustrates a single line diagram of a switching circuit according to an embodiment presented herein;

Fig. 3 schematically illustrates a single line diagram of a switching circuit according to an alternative embodiment presented herein;

Figs. 4-9 schematically illustrate normal load transfer according to an embodiment presented herein; Fig. 10 schematically shows a flow chart for the normal load transfer illustrated in Figs. 4-9;

Figs. 11-14 schematically illustrate reverse load transfer according to an embodiment presented herein; Fig. 15 schematically shows a flow chart for the reverse load transfer illustrated in Figs. 11-14;

Figs. 16-17 schematically illustrate load fault handling according to an embodiment presented herein;

Fig. 18 schematically shows a flow chart for the load fault handling illustrated in Figs. 16-17;

Figs. 19-20 schematically illustrate FCS fault handling according to an embodiment presented herein;

Fig. 21 schematically shows a flow chart for the FCS fault handling illustrated in Figs. 19-20; Fig. 22 schematically illustrates a maintenance bypass according to an embodiment presented herein; and

Fig. 23 schematically illustrates commutation assistance according to an embodiment presented herein.

DETAILED DESCRIPTION

The invention will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout the description. A Low Loss Static Transfer Switch (LLSTS) for use in ac power supply, e.g. for data centre applications or similar load sensitive applications, is presented.

A regular Static Transfer Switch (STS) operates when a fault in supply voltage is detected and responds by transferring a sensitive load to an alternative supply voltage.

A Fast mechanical Commutating Switch (FCS) is used in combination with an STS. The FCS is a very fast mechanical switch that cannot break current but can commutate current into a parallel path, the STS. It is able to open and to commutate the current from the FCS into the STS. The FCS also further enables use of forced commutating power electronic switches which has higher conduction losses compared to line commutated power electronic switches. Forced commutating switches have potential to improve the speed of the STS and possibly manage more transfer conditions.

The use of FCS also provides potential to increase uptime as the

semiconductors are only thermally stressed during short periods of the lifetime of the LLSTS.

The present invention is described for medium voltage applications (1-35 kV), but the principle can be used in both low voltage (50-1000 V) and high voltage (>35 kV) applications using STS and as well. The ac power supply to data centre applications often includes an STS. In case of a disturbance of the supply voltage, the switch is used to transfer the data centre load to a secure alternative supply voltage within a relatively short period of time.

Three drawbacks with the use of an STS are: · losses cost availability The present invention alleviates all of the three above mentioned problems with an STS, specifically the losses.

An STS that is conducting during normal operation continuously produces conduction heat losses and the switch requires a cooling system. Normally, line commutating switches such as thyristors or semiconductor- controlled rectifiers (SCRs) are used in an STS. It is also possible to use forced commutated switches instead of line commutated switches such as Integrated gate-commutated thyristors (IGCTs), Insulated-gate bipolar transistors (IGBTs) or Bi-mode Insulated Gate Transistors (BIGTs). The use of forced commutating switches can improve the speed of the transfer and can possibly manage more transfer conditions as the forced commutating switch does not need to wait for a zero current crossing condition. Forced commutating switches have however even higher conduction losses than the line commutating switches, which limits their use. The problem with high losses of an STS is however removed during normal operation according to the present invention.

STS losses during normal operation typically require a cooling system such as liquid cooling or forced air cooling to be used. This results in a cost both for initial investment cost but also operational cost by losses and maintenance. The active use time of an STS is significantly reduced according to the present invention, and the use of liquid or forced air cooling is obviated.

E.g. data centres usually have a very high availability requirement.

Semiconductor breakers have a limited lifetime compared to a traditional circuit breaker. The active use time of an STS is significantly reduced according to the present invention, and the total lifetime is thus significantly increased.

A protection and control system may further be used to synch the FCS with the STS according to the present invention. A LLSTS circuit single line diagram, according to an embodiment, is illustrated in Fig. 2. The components in Fig. 2 are the following.

Vsourcei represents normal ac supply voltage, e.g. a grid network.

V _S ource2 represents alternative ac supply voltage, e.g. a grid network or a UPS with a converter or a generator.

Lsi represents system inductance of V _SO urcei.

Ls2 represents system inductance of V _SO urce2.

Lsci represents system inductance between a potential fault and the LLSTS.

Lgi represents system ground inductance between a potential fault and the LLSTS.

RLI represents a resistive part of a load, such as a data centre load.

LLI represents an inductive part of a load, such as a data centre load.

Si represents a switch which forms a part of the STS of the LLSTS. It comprises one or several line commutating switches in series such as thyristors, or one or several forced commutating switches in series such as reverse blocking IGCTs. With the use of a reverse conducting IGCT, an IGBT, BIGT, etc. (having an anti-parallel diode) the Si would be in series with S ₂ (in opposite direction of each other) instead of in parallel as illustrated in the drawings. S ₂ represents a switch which forms a part of the STS of the LLSTS. It comprises one or several line commutating switches in series such as thyristors, or one or several forced commutating switches in series such as reverse blocking IGCTs. With the use of a reverse conducting IGCT, an IGBT, BIGT, etc. (having an anti-parallel diode) the Si would be in series with S ₂ (in opposite direction of each other) instead of in parallel as illustrated in the drawings. FCSi represents an FCS which forms a part of the LLSTS.

Ri represents a resistive part in a snubber circuit, which may form a part of the LLSTS.

Ci represents a capacitive part in a snubber circuit, which may form a part of the LLSTS.

Rai represents a surge arrester or varistor to limit the voltage across the LLSTS, which may form a part of the LLSTS.

QA ₂ represents a control of the alternative voltage source Vsource2. This can e.g. be a breaker, another LLSTS (as illustrated in Fig. 3), an STS, a converter control function or similar.

An FCS is used in combination with an STS connected in parallel. In Fig. 2 this is illustrated with FCSi, Si, S ₂ and possible accompanying components such as Ri, Ci and Rai. An additional snubber resistor may be used across Si and S ₂ depending on the system characteristics. To illustrate with an example of the reduction of losses with the illustrated embodiment, an estimation is made and compare a breaker with a

semiconductor.

The equivalent resistance will depend on the semiconductor, type of breaker and breaker material, breaker contact pressure, current and voltage, etc. A sinusoidal rms (root mean square) current of I _rm s = 1000 A to the load is assumed. Further, a resistance of 0.1 mft is assumed in the breaker. This results in power losses of P = = 0.1 mft x (1000 A) ² = 100 W. For three phases this results in 300 W.

To compare, assuming a valve of bi-directional thyristor semiconductors with each thyristor having a voltage threshold of VT = 1 V and slope resistance of rr = 0.6 mfl. Further, it is assumed that the system voltage conditions requires 5 thyristors in series in the valve. Each thyristor will approximately experience an average current of IT ,avg — Irms x 2 / π = 450 A and a rms current of IT ,rms— Irms / V2 = 707 A. This results in a power loss of about Ρτ = VT*lT,av _g +rT* _,rms = iV*45oA+o.6mil*(707

A) ² =750 W. Having a bi-directional valve and five thyristors in series and three phases equates to Ptot=PT*2*5*3=22 500 W. The loss reduction using the breaker in this case would be (22 500 W - 300 W) / 22 500 W « 99%.

As mentioned above, the exact loss reduction depends on the breaker characteristics, semiconductor characteristics and the system characteristics. However, it shows that a significant benefit can be made for similar systems. Furthermore, the use of an FCS removes the disadvantage of the higher conduction losses of forced commutating switches.

Since the STS in such a setup would not have conduction losses and only has a limited amount of switching, there should not be any need for a liquid or air forced cooling system. Therefore the cost and maintenance of the cooling system of the STS, including fans and pumps, should as well disappear.

The availability has potential to increase due to that the current is not passing through the semiconductors during most of the LLSTS lifetime. This reduces for example mechanical stress as there is no significant thermal cycling.

Transfer time IEC 62040-3 categorizes dynamic output performance requirements on UPS systems. General purpose IT loads such as switched mode power supplies are categorized as "Class 3". An example is that Class 3 requires a transfer duration within 10 ms for a 100 % voltage drop. For voltage drops less than 100 %, the transfer time is allowed to be higher. The transfer duration consists of detection of a voltage drop and performance of the actual transfer. The detection time can vary dependent on the event and the detection system. A detection system may e.g. require up to 10 ms (using a 20 % voltage drop and threshold of 0.7 p.u. (per unit)) or even go undetected.

An FCS switch is able to commutate the current from the FCSi to Si or S ₂ in about 0.5 ms. The commutation time will depend on the system

characteristics, FCS arc voltage, inductance in the FCS and Si & S ₂ loop, and the voltage drop in the Si and S ₂ valve.

The additional commutation time using the FCS is fairly negligible in respect to the total transfer time.

Normal load transfer is illustrated in Figs. 4-9. In normal operation, as illustrated in Fig. 4, the load is supplied from the

Vsourcel via the FCSi. FCSi is closed and Si and S ₂ are open, i.e. not turned on.

A fault condition occurs, illustrated in Fig. 5, at the supply voltage side at node 1. The V _SO urcei will feed this fault with a fault current, represented by loop Li. Depending on the inductance in the load and the inductance between the fault and the STS, a current will continue to flow in the load, represented by loop L ₂ .

In Fig. 6, the fault is detected by a control system (not illustrated), Si is closed (turned on) and the FCSi is started to be opened, creating an arc voltage that starts commutating the load current from the FCSi to the Si, represented by loop L ₃ . Expected commutation time of the FCSi to Si is about 0.5 ms.

The current has in Fig. 7 finished commutating and the arc in FCSi disappears. FCSi is now open with sufficient voltage withstand due to no more existing arc. The condition is now similar to a standard STS.

In Fig. 8 the alternative source V _SO urce ₂ starts to conduct and supply current to both the load and the fault, represented by loops L ₄ and L ₅ . The current in Si will eventually reach a zero crossing due to the voltage potential difference between V _SO urce ₂ and node 1. In case of using thyristors, they can now interrupt the current at the current zero crossing. In the case of V _SO urce2 not being controllable, i.e. a mechanical switch QA ₂ does not exist, there may be increased risk of a transfer delay when thyristors are used in the STS. For e.g. a case when V _SO urcei and V _SO urce2 are not in phase with each other, or when the load does not have a phase factor of 1, there is a risk that the transfer is delayed. The current through the STS may then have finished reversing before turning off Si. In this case, it would be beneficial to use forced commutated switches instead of thyristors.

The Si is now open (turned off) and the load is only supplied from V _SO urce2, which is illustrated in Fig. 9. The normal load transfer described with reference to Figs. 4-9, is illustrated in a flow chart in Fig. 10.

Reverse load transfer, i.e. transfer back to the main supply source from the alternative supply source, is illustrated in Figs. 11-14.

The load is in Fig. 11 supplied from alternative SOUrce Vsource2. Vsourcei and Vsource2 are preferably synched with each other.

In Fig. 12 are Si and S ₂ closed (turned on) and both V _SO urcei and V _SO urce2 are supplying the load. Alternatively FCSi is closed. Turning on Si and S ₂ , while keeping FCSi open, is preferred in case of a remaining fault on Vsourcei, enabling a fast current interruption by Si or S ₂ . In Fig. 13 QA ₂ is opened and the load is now supplied only from Vsourcei.

FCSi is closed, illustrated in Fig. 14, and Si and S ₂ can be opened (turned off).

The reverse load transfer described with reference to Figs. 11-14 is illustrated in a flow chart in Fig. 15.

A fault at the load may further be detected, and handled by an upstream breaker, illustrated by QAi.

In Fig. 16 a fault is detected at the load side at node 4. In Fig. 17 the upstream breaker QAi is opened and the fault is isolated. The control and protection system should detect a high short circuit current or current derivative flowing through the FCSi and wait for an upstream breaker to disconnect the fault. If this detection condition cannot be fulfilled due to system characteristics, either the STS needs to be able to manage the short circuit current or the FCSi could be closed again during the short circuit if within design parameters of the FCSi. If forced commutating power electronic switches are used in the STS, the STS may break the short circuit itself.

Fig. i8 shows a flow chart sequence of the fault at the load side at node 4, described with reference to Figs. 16 and 17.

Further, in case of a failure of the FCS into open circuit in normal operation, a detection system may potentially detect an abnormal voltage across the LLSTS and turn on (close) Si and S ₂ . Without a cooling system, the LLSTS may initiate a transfer of the load to the alternative voltage source.

Optionally, with a cooling system of the LLSTS, it would then function as a standard STS until the FCS is repaired or replaced.

A fault at the FCS into open circuit is detected in Fig. 19. In Fig. 20 Si and S ₂ are turned on (closed) and a transfer to V _SO urce2 is initiated.

A flow chart sequence the fault of the FCS into open circuit, described with reference to Figs. 19 and 20, is illustrated in Fig. 21.

A maintenance bypass switch may optionally be used in combination with disconnectors to perform maintenance on the LLSTS similar to a bypass switch illustrated in Fig. 1.

Fig. 22 shows a single line diagram of the circuit setup with a maintenance bypass switch. The additional components are the following.

QBi represents a disconnector forming a part of the maintenance switch.

QB ₂ represents a disconnector forming a part of the maintenance switch. QB ₃ represents a disconnector forming a part of the maintenance switch.

For high voltage applications, it is possible that the arc voltage from the FCS will not be large enough for a fast commutation from the FCS to the STS. In such a case a semiconductor may be added in series with the FCS. Fig. 23 illustrates a single line diagram of the circuit setup with commutation assistance. The commutation assistance will in this case need to be of a kind that breaks current before a zero crossing, such as IGBT.

The additional components in Fig. 23 are the following.

S ₅ represents a forced commutating switch such as an IGCT, IGBT or BIGT. S ₆ represents a forced commutating switch such as an IGCT, IGBT or BIGT.

A system that combines an STS and an FCS together, e.g. for use in data centre applications, is presented. Conduction losses are negligible, and it is further possible to use forced commutating switches and to remove the requirement of a cooling system for the STS. The system may use a protection and control system that controls and synchs the FCS with the STS. The control and protection system detects what type of fault occurs and takes decision if e.g. an upstream breaker should clear the fault or if the FCS should commutate the load current to the STS. In case of not fulfilling detection requirements for a fault at the load side and if within design parameters, the control system may decide to re-close FCSi.

The LLSTS may be used together with an alternative load such as a grid network, a UPS or a generator. A controllable source such as a converter may assist in the load transfer. The voltage phase angle of V _SO urce2 may for a controllable source e.g. be adjusted to compensate for variations in the current direction in line commutated switches to ensure a fast turn off.

The invention has mainly been described above with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the invention, as defined by the appended patent claims.