Title:
LOGIC INTEGRATED CIRCUIT AND WRITING METHOD
Document Type and Number:
WIPO Patent Application WO/2019/208414
Kind Code:
A1
Abstract:
In order to provide a logic integrated circuit capable of writing and erasing data to and from a resistance change element requiring a high voltage without electrically destroying a micro-semiconductor element, the logic integrated circuit is provided with: a switch block having multiple first wires extending in a first direction, multiple second wires extending in a second direction intersecting the first direction, at least one redundant wire extending in the second direction along the second wires, and multiple resistance change elements arranged in the form of a matrix at positions where the second wires and the redundant wire intersect with the first wires; a transfer block having multiple buffers respectively connected to multiple third wires extending in the second direction in a corresponding manner to the multiple second wires; and a shift block having multiple switching circuits respectively corresponding to the multiple second wires and each having a high-withstand voltage transistor, thereby switching connections of the second wires and the redundant wire with the third wires in accordance with voltage states of selection terminals respectively corresponding to the multiple switching circuits.
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Inventors:
TADA AYUKA (JP)
NEBASHI RYUSUKE (JP)
TSUJI YUKIHIDE (JP)
SAKAMOTO TOSHITSUGU (JP)
MIYAMURA MAKOTO (JP)
BAI XU (JP)
NEBASHI RYUSUKE (JP)
TSUJI YUKIHIDE (JP)
SAKAMOTO TOSHITSUGU (JP)
MIYAMURA MAKOTO (JP)
BAI XU (JP)
Application Number:
PCT/JP2019/016754
Publication Date:
October 31, 2019
Filing Date:
April 19, 2019
Export Citation:
Assignee:
NEC CORP (JP)
International Classes:
H03K19/177; G11C13/00; H01L21/82; H01L21/8239; H01L27/105; H01L45/00; H01L49/00
Foreign References:
| JP2016225797A | 2016-12-28 | |||
| JP2016129081A | 2016-07-14 |
Attorney, Agent or Firm:
SHIMOSAKA Naoki (JP)
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